SN74LS74A
AC WAVEFORMS
D*
1.3 V
t
h(L)
t
s(L)
1.3 V
t
W(H)
1.3 V
t
h(H)
t
s(H)
t
W(L)
1.3 V
1
f
MAX
CP
t
PHL
Q
1.3 V
t
PHL
t
PLH
1.3 V
t
PLH
1.3 V
Q
1.3 V
*The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays, Data
Set-Up and Hold Times, Clock Pulse Width
t
W
SET
1.3 V
1.3 V
t
W
CLEAR
t
PLH
1.3 V
t
PHL
Q
1.3 V
t
PHL
1.3 V
t
PLH
1.3 V
Q
1.3 V
1.3 V
Figure 2. Set and Clear to Output Delays,
Set and Clear Pulse Widths
http://onsemi.com
4