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MC10131L 参数 Datasheet PDF下载

MC10131L图片预览
型号: MC10131L
PDF下载: 下载PDF文件 查看货源
内容描述: 双D型主从触发器 [Dual Type D Master-Slave Flip-Flop]
分类和应用: 触发器
文件页数/大小: 8 页 / 113 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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MC10131
ELECTRICAL CHARACTERISTICS
(continued)
TEST VOLTAGE VALUES
(Volts)
@ Test Temperature
–30°C
+25°C
+85°C
Pin
Under
Test
8
4
5
6
7
9
4, 5*
6, 7, 9*
2
2[
2
3[
2
2[
2
3[
+1.11Vdc
Propagation Delay
t
9+2–
t
9+2+
t
6+2+
t
6+2–
t
2+
t
2–
2
2
2
2
2
2
7
7
7
5
7
5
7
5
7
5
7
Pulse In
9
9
6
6
9
9
9
9
Pulse Out
2
2
2
2
2
2
4
5
6
7
9
*
*
V
IHmax
–0.890
–0.810
–0.700
V
ILmin
–1.890
–1.850
–1.825
V
IHAmin
–1.205
–1.105
–1.035
V
ILAmax
–1.500
–1.475
–1.440
V
EE
–5.2
–5.2
–5.2
(V
CC
)
Gnd
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
+2.0 V
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
EE
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
–3.2 V
8
8
8
8
8
8
Characteristic
Power Supply Drain Current
Input Current
Symbol
I
E
I
inH
I
inL
Output Voltage
Output Voltage
Threshold Voltage
Threshold Voltage
Switching Times
Clock Input
Logic 1
Logic 0
Logic 1
Logic 0
(50Ω Load)
V
OH
V
OL
V
OHA
V
OLA
Rise Time
Fall Time
Set Input
(20 to 80%)
(20 to 80%)
Propagation Delay
t
5+2+
t
12+15+
t
5+3–
t
12+14–
2
15
3
14
6
9
5
12
5
12
2
15
3
14
8
8
8
8
1, 16
1, 16
1, 16
1, 16
Reset Input
Propagation Delay
t
4+2–
t
13+15–
t
4+3–
t
13+14+
t
setup
t
hold
f
tog
2
15
3
14
7
7
2
6
9
4
13
4
13
6, 7
6, 7
6
2
15
3
14
2
2
2
V
IHmax
V
ILmin
8
8
8
8
8
8
8
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
Setup Time
Hold Time
Toggle Frequency (Max)
* Individually test each input applying V
IH
or V
IL
to input under test.
[
Output level to be measured after a clock pulse has been applied to the C
E
Input (Pin 6)
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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