MC14490
Hex Contact Bounce
Eliminator
The MC14490 is constructed with complementary MOS
enhancement mode devices, and is used for the elimination of
extraneous level changes that result when interfacing with mechanical
contacts. The digital contact bounce eliminator circuit takes an input
signal from a bouncing contact and generates a clean digital signal
four clock periods after the input has stabilized. The bounce eliminator
circuit will remove bounce on both the “make” and the “break” of a
contact closure. The clock for operation of the MC14490 is derived
from an internal R–C oscillator which requires only an external
capacitor to adjust for the desired operating frequency (bounce delay).
The clock may also be driven from an external clock source or the
oscillator of another MC14490 (see Figure 5).
NOTE: Immediately after power–up, the outputs of the MC14490
are in indeterminate states.
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
1
16
SOIC–16
DW SUFFIX
CASE 751G
1
16
SOEIAJ–16
F SUFFIX
CASE 966
MC14490
AWLYWW
14490
MC14490P
AWLYYWW
•
•
•
•
•
•
•
•
•
•
•
•
Diode Protection on All Inputs
Six Debouncers Per Package
Internal Pullups on All Data Inputs
Can Be Used as a Digital Integrator, System Synchronizer, or Delay
Line
Internal Oscillator (R–C), or External Clock Source
TTL Compatible Data Inputs/Outputs
Single Line Input, Debounces Both “Make” and “Break” Contacts
Does Not Require “Form C” (Single Pole Double Throw) Input
Signal
Cascadable for Longer Time Delays
Schmitt Trigger on Clock Input (Pin 7)
Supply Voltage Range = 3.0 V to 18 V
Chip Complexity: 546 FETs or 136.5 Equivalent Gates
AWLYYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
MC14490DW
Package
SOIC–16
SOIC–16
SOEIAJ–16
SOEIAJ–16
PDIP–16
Shipping
47/Rail
1000/Tape & Reel
See Note 1.
See Note 1.
25/Rail
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
V
DD
V
in
, V
out
I
in
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 3.)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8–Second Soldering)
Value
– 0.5 to +18.0
– 0.5 to V
DD
+ 0.5
±
10
500
– 55 to +125
– 65 to +150
260
Unit
V
V
mA
mW
°C
°C
°C
MC14490DWR2
MC14490F
MC14490FEL
MC14490P
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid ap-
plications of any voltage higher than maximum rated
voltages to this high–impedance circuit. For proper
operation, V
in
and V
out
should be constrained to the
range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either V
SS
or V
DD
). Unused out-
puts must be left open.
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
v
v
©
Semiconductor Components Industries, LLC, 2000
1
May, 2000 – Rev. 4
Publication Order Number:
MC14490/D
ONSEMI [ ON SEMICONDUCTOR ]
