MC14504B
Hex Level Shifter for TTL to
CMOS or CMOS to CMOS
The MC14504B is a hex non−inverting level shifter using CMOS
technology. The level shifter will shift a TTL signal to CMOS logic
levels for any CMOS supply voltage between 5 and 15 volts. A control
input also allows interface from CMOS to CMOS at one logic level to
another logic level: Either up or down level translating is
accomplished by selection of power supply levels V
DD
and V
CC
. The
V
CC
level sets the input signal levels while V
DD
selects the output
voltage levels.
Features
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
16
MC14504BCP
AWLYYWWG
1
•
UP Translates from a Low to a High Voltage or DOWN Translates
•
•
•
•
•
•
from a High to a Low Voltage
Input Threshold Can Be Shifted for TTL Compatibility
No Sequencing Required on Power Supplies or Inputs for Power Up
or Power Down
3 to 18 Vdc Operation for V
DD
and V
CC
Diode Protected Inputs to V
SS
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Pb−Free Packages are Available*
Parameter
DC Supply Voltage Range
DC Supply Voltage Range
Input Voltage Range
(DC or Transient)
Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
Value
−0.5 to +18.0
−0.5 to +18.0
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±
10
500
−55 to +125
−65 to +150
260
Unit
V
V
V
V
mA
mW
°C
°C
°C
16
SOIC−16
D SUFFIX
CASE 751B
1
14504BG
AWLYWW
16
TSSOP−16
DT SUFFIX
CASE 948F
1
14
504B
ALYW
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
CC
V
DD
V
in
V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
16
SOEIAJ−16
F SUFFIX
CASE 966
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
MC14504B
ALYWG
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
©
Semiconductor Components Industries, LLC, 2005
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
1
August, 2005 − Rev. 6
Publication Order Number:
MC14504B/D
ONSEMI [ ON SEMICONDUCTOR ]
