SN74LS175
CONNECTION DIAGRAM DIP
(TOP VIEW)
V
CC
16
Q
3
15
Q
3
14
D
3
13
D
2
12
Q
2
11
Q
2
10
CP
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
MR
2
Q
0
3
Q
0
4
D
0
5
D
1
6
Q
1
7
Q
1
8
GND
LOADING
(Note a)
PIN NAMES
D
0
– D
3
CP
MR
Q
0
– Q
3
Q
0
– Q
3
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
True Outputs
Complemented Outputs
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
m
A HIGH/1.6 mA LOW.
LOGIC SYMBOL
4
5
12
13
9
CP
D
0
D
1
D
2
D
3
1
MR
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
3
2
6
7
11
10 14 15
V
CC
= PIN 16
GND = PIN 8
LOGIC DIAGRAM
MR CP D
3
1
9
13
D
2
12
D
1
5
D
0
4
D Q
CP Q
C
D
14
15
D Q
CP Q
C
D
11
10
D Q
CP Q
C
D
6
7
D Q
CP Q
C
D
3
2
Q
3
Q
3
Q
2
Q
2
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
Q
1
Q
1
Q
0
Q
0
http://onsemi.com
2
ONSEMI [ ON SEMICONDUCTOR ]
