Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G80
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 °C to +125 °C
VIH
HIGH-level input
voltage
1.65 to 1.95 0.65 × VCC
−
−
−
−
−
−
−
−
−
−
−
−
V
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.7
V
V
V
V
V
V
V
2.0
0.7 × VCC
VIL
LOW-level input
voltage
−
−
−
−
0.35 × VCC
0.7
0.8
0.3 × VCC
VOL
LOW-level output
voltage
VI = VIH or VIL
IO = 100 µA
IO = 4 mA
1.65 to 5.5
1.65
2.3
−
−
−
−
−
−
−
−
−
−
−
−
0.1
V
V
V
V
V
V
0.7
IO = 8 mA
0.45
0.60
0.80
0.80
IO = 12 mA
IO = 24 mA
IO = 32 mA
VI = VIH or VIL
IO = −100 µA
IO = −4 mA
IO = −8 mA
IO = −12 mA
IO = −24 mA
IO = −32 mA
2.7
3.0
4.5
VOH
HIGH-level output
voltage
1.65 to 5.5
1.65
2.3
V
CC − 0.1
−
−
−
−
−
−
−
−
−
V
0.95
1.7
1.9
2.0
3.4
−
−
V
−
V
2.7
−
V
3.0
−
V
4.5
−
V
ILI
input leakage current
VI = 5.5 V or GND 5.5
VI or VO = 5.5 V
±100
±200
µA
µA
Ioff
power OFF leakage
current
0
−
ICC
quiescent supply
current
VI = VCC or GND; 5.5
IO = 0 A
−
−
−
−
200
µA
µA
∆ICC
additional quiescent
supply current per
input pin
VI = VCC − 0.6 V;
2.3 to 5.5
5000
IO = 0 A
Note
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2004 Sep 10
8
PANASONIC [ PANASONIC ]
