PE4273
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4273 SPDT switch. The RF common port is
connected through a 75
Ω
transmission line to the
bottom F connector, J2. Port 1 and Port 2 are
connected through 75
Ω
transmission lines to two F
connectors on either side of the board, J3 and J1. A
through transmission line connects F connectors J4
and J5. This transmission line can be used to
estimate the loss of the PCB over the environmental
conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The bottom
layer provides ground for the RF transmission lines.
The transmission lines were designed using a
coplanar waveguide with ground plane model using
a trace width of 0.021”, trace gaps of 0.030”,
dielectric thickness of 0.028”, copper thickness of
0.0021” and
ε
r
of 4.3.
J6 and J7 provide a means for controlling the DC
inputs to the device. The lower left header (J6) is
connected to the device V1 input. The lower right
header (J7) is connected to the device V2 input.
Series resistors (R1 and R2) are provided to reduce
the package resonance between RF and DC lines.
Footprints for decoupling capacitors (100 pF) are
provided on both V1 and V2 traces. It is the
responsibility of the customer to determine proper
supply decoupling for their design application.
Removing these components from the evaluation
board has not been shown to degrade RF
performance.
Figure 5. Evaluation Board Layouts
Peregrine Specification 101/0245
Figure 6. Evaluation Board Schematic
Peregrine Specification 102/0311
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 10
Document No. 70-0174-03
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UltraCMOS™ RFIC Solutions
PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
