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4309-51 参数 Datasheet PDF下载

4309-51图片预览
型号: 4309-51
PDF下载: 下载PDF文件 查看货源
内容描述: 50ヘ射频数字衰减器6位, 31.5分贝, DC- 4.0 GHz的 [50 ヘ RF Digital Attenuator 6-bit, 31.5 dB, DC-4.0 GHz]
分类和应用: 射频衰减器
文件页数/大小: 9 页 / 338 K
品牌: PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
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Product Specification
PE4309
Product Description
This product is a high linearity, 6-bit RF Digital Step Attenuator
(DSA) covering a 31.5 dB attenuation range in 0.5 dB steps.
The Peregrine 50Ω RF DSA provides a parallel CMOS control
interface and it operates on 3-volt to 5-volt supply. It maintains
high attenuation accuracy over frequency and temperature and
exhibits very low insertion loss and low power consumption.
This Peregrine DSA is available in a 4x4 mm 24 lead QFN
footprint with an exposed ground paddle.
The PE4309 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Schematic Diagram
Switched Attenuator Array
RF Input
RF Output
50
RF Digital Attenuator
6-bit, 31.5 dB, DC-4.0 GHz
Features
Best in class 2.0 kV HBM ESD tolerance
Low Insertion Loss: 1.6 dB typical
Attenuation: 0.5 dB steps to 31.5 dB
High Linearity: Typical 52 dB IP3
Best in Class Attenuation accuracy
Parallel programming interface
Single supply, 3V to 5V operation
Standard 3V or 5V CMOS control logic
independent of supply voltage
Very low power consumption
RoHS-compliant 24-lead 4x4 mm QFN
Figure 2. Package Type
4x4 mm 24-Lead QFN
Parallel Control
6
Control Logic Interface
Table 1. Electrical Specifications @ +25°C, V
DD
= 3.0 V - 5.0 V
Parameter
Operation Frequency
Insertion Loss
Any Bit or Bit Combination
Any Bit or Bit Combination
0.5 - 7.5 dB States
3
8.0 - 15.5 dB States
3
16.0 - 31.5 dB States
3
DC - 2.2 GHz
2.2 - 4.0 GHz
DC
1.0 GHz
1.0 < 2.2 GHz
2.2 < 3.8 GHz
2.2 < 3.8 GHz
2.2 < 3.8 GHz
1 MHz - 2.2 GHz
2.2 - 4.0 GHz
Two-tone inputs +18 dBm
1 MHz - 2.2 GHz
2.2 - 4.0 GHz
DC - 2.2 GHz
2.2 - 4.0 GHz
50% of control voltage to
90% of final attenuation level
Test Conditions
4
Frequency
Min
DC
-
-
-
-
-
-
-
30
-
-
-
15
10
-
Typ
1.6
2.2
-
-
0.15
0.7
1.2
32
32
52
45
20
20
-
Maximum
4000
2
3.4
±(0.10 + 3% of atten setting), not to exceed +0.20 dB
±(0.15 + 3% of atten setting)
-
-
-
-
-
-
-
-
-
1
Units
MHz
dB
dB
dB
dB
dB
dB
dB
dBm
dBm
dBm
dBm
dB
dB
µs
Attenuation Accuracy
1 dB Compression
2
Input IP3
1
Return Loss
Switching Speed
Notes: 1.
2.
3.
4.
Device Linearity will begin to degrade below 5 MHz.
Note Absolute Maximum in Table 4.
See Figures 12 and 13 for typical attenuation error.
Measurements made in a 50 ohm system (see Figure 4, Test Circuit Block Diagram). Resistors (R2, R3, R5, R6, R7) with a
value of 10K-ohm are used to decouple the RF path from the control inputs.
©2007 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 9
Document No. 70-0218-06
www.psemi.com