PE9701
Product Specification
Serial Interface Mode
Serial Interface Mode is selected by setting the
Bmode
input “low” and the Smode input “high”.
While the E_WR input is “low” and the S_WR
input is “low”, serial input data (Sdata input), B
0
to
B
19
, is clocked serially into the primary register on
the rising edge of Sclk, MSB (B
0
) first. The
contents from the primary register are transferred
into the secondary register on the rising edge of
either S_WR or Hop_WR according to the timing
diagram shown in Figure 6. Data is transferred to
the counters as shown in Table 7 on page 9.
The double buffering provided by the primary and
secondary registers allows for “ping-pong” counter
control using the FSELS input. When FSELS is
“high”, the primary register contents set the
counter inputs.
When FSELS is “low”, the
secondary register contents are utilized.
While the E_WR input is “high” and the S_WR
input is “low”, serial input data (Sdata input), B
0
to
Table 7. Primary Register Programming
Interface
Mode
Parallel
Serial*
Direct
Enh
Bmode
Smode
R
5
R
4
M
8
M
7
Pre_en
M
6
M
5
M
4
B
7
, is clocked serially into the enhancement
register on the rising edge of Sclk, MSB (B
0
) first.
The enhancement register is double buffered to
prevent inadvertent control changes during serial
loading, with buffer capture of the serially-entered
data performed on the falling edge of E_WR
according to the timing diagram shown in Figure
6. After the falling edge of E_WR, the data
provides control bits as shown in Table 8 with bit
functionality enabled by asserting the
Enh
input
“low”.
Direct Interface Mode
Direct Interface Mode is selected by setting the
Bmode
input “high”.
Counter control bits are set directly at the pins as
shown in Table 7. In Direct Interface Mode, main
counter inputs M
7
and M
8
, and R Counter inputs
R
4
and R
5
are internally forced low (“0”).
M
3
M
2
M
1
M
0
R
3
R
2
R
1
R
0
A
3
A
2
A
1
A
0
1
1
1
0
0
1
0
1
X
M2_WR rising edge load
D
3
B
0
0
D
2
B
1
0
D
1
B
2
0
D
0
B
3
0
D
7
B
4
Pre_en
D
6
B
5
M
6
M1_WR rising edge load
D
5
B
6
M
5
D
4
B
7
M
4
D
3
B
8
M
3
D
2
B
9
M
2
D
1
B
10
M
1
D
0
B
11
M
0
D
7
B
12
R
3
D
6
B
13
R
2
A_WR rising edge load
D
5
B
14
R
1
D
4
B
15
R
0
D
3
B
16
A
3
D
2
B
17
A
2
D
1
B
18
A
1
D
0
B
19
A
0
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface
Mode
Parallel
Enh
Bmode
Smode
Reserved
Reserved
Reserved
Power
down
Counter
load
MSEL
output
Prescaler
output
f
c
, f
p
OE
E_WR rising edge load
0
0
0
D
7
B
0
D
6
B
1
D
5
B
2
D
4
B
3
D
3
B
4
D
2
B
5
D
1
B
6
D
0
B
7
Serial*
0
0
1
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
MSB (first in)
(last in) LSB
Document No. 70-0035-02
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©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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