Product Specification
PE42510A
Product Description
The following specification defines an SPDT (single pole
double throw) switch for use in cellular and other wireless
applications. The PE42510A uses Peregrine’s UltraCMOS™
process and it also features HaRP™ technology
enhancements to deliver high linearity and exceptional
harmonics performance. HaRP™ technology is an innovative
feature of the UltraCMOS™ process providing upgraded
linearity performance.
The PE42510A is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Diagram
RFC
SPDT High Power UltraCMOS™
RF Switch 30 - 2000 MHz
Features
•
No blocking capacitors required
•
50 Watt P1dB compression point
•
10 Watts <8:1 VSWR (Normal
Operation)
•
29 dB Isolation @800 MHz
•
< 0.3 dB Insertion Loss at 800 MHz
•
2f
o
and 3f
o
< -84 dBc @ 42.5 dBm
•
ESD rugged to 2.0 kV HBM
•
32-lead 5x5 mm QFN package
Figure 2. Package Type
32-lead 5x5 mm QFN
RF1
RF2
CMOS
Control Driver
and ESD
CTRL
Table 1. Electrical Specifications @ 25 °C, V
DD
= 3.3 V
(Z
S
= Z
L
= 50
Ω
) unless otherwise noted
Parameter
RF Insertion Loss
0.1 dB Input Compression Point
Isolation (Supply Biased): RF to RFC
Unbiased Isolation: RF - RFC, V
DD
, V1=0 V
RF (Active Port) Return Loss
2nd Harmonic
3rd Harmonic
Switching Time
Lifetime switch cycles
800 MHz @ +42.5 dBm
50% of CTRL to 10/90% of RF
No RF applied
30 MHz
≤
1 GHz
1 GHz < 2 GHz
800 MHz, 50% duty cycle
800 MHz
27 dBm, 800 MHz
25
5
15
22
-84
0.04
10^10
-81
0.5
Conditions
Min
Typ
0.4
0.5
45.4
29
Max
0.6
0.7
Units
dB
dB
dBm
dB
dB
dB
dBc
ms
cycles
Note: The device was matched with 1.6 nH inductance per RF port
Document No. 70-0266-01
│
www.psemi.com
©2008 Peregrine Semiconductor Corp. All rights reserved.
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