PE4306
Product Specification
Figure 14. Pin Configuration (Top View)
GND
N/C
C1
C2
C4
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
Parameter/Conditions
Power supply voltage
Voltage on any DC input
Storage temperature range
Input power (50Ω)
ESD voltage (Human Body
Model)
Min
-0.3
-0.3
-65
Max
4.0
V
DD
+
0.3
150
+30
500
Units
V
V
°C
dBm
V
20
19
18
17
16
C16
RF1
Data
Clock
LE
1
2
3
4
5
10
15
C8
RF2
P/S
Vss/GND
GND
T
ST
P
IN
V
ESD
20-lead
QFN
4x4 mm
Exposed Solder Pad
14
13
12
11
V
DD
V
DD
PUP1
PUP2
GND
Exceeding absolute maximum ratings may cause per-
manent damage. Operation should be restricted to the
limits in the Operating Ranges table. Operation be-
tween operating range maximum and absolute maxi-
mum for extended periods may reduce reliability.
6
7
8
9
Table 2. Pin Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Paddle
Table 4. Operating Ranges
Parameter
Description
Min
2.7
Pin
Name
C16
RF1
Data
Clock
LE
V
DD
PUP1
PUP2
V
DD
GND
GND
V
ss
/GND
P/S
RF2
C8
C4
C2
GND
C1
N/C
GND
Typ
3.0
Max
3.3
100
Units
V
µA
V
Attenuation control bit, 16 dB (Note 4).
RF port (Note 1).
Serial interface data input (Note 4).
Serial interface clock input.
Latch Enable input (Note 2).
Power supply pin.
Power-up selection bit.
Power-up selection bit.
Power supply pin.
Ground connection.
Ground connection.
Negative supply voltage or GND connection
(Note 3)
Parallel/Serial mode select.
RF port (Note 1).
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Attenuation control bit, 1 dB.
No connect. Can be connected to any bias.
Ground for proper operation
V
DD
Power Supply
Voltage
I
DD
Power Supply
Current
Digital Input High
Digital Input Low
Digital Input Leakage
Input Power
Temperature range
0.7xV
DD
0.3xV
DD
1
+24
-40
85
V
µA
dBm
°C
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™ de-
vices are immune to latch-up.
Switching Frequency
The PE4306 has a maximum 25 kHz switching rate.
Resistor on Pin 1 & 3
A 10 kΩ resistor on the inputs to Pin 1 & 3 (see Figure
16) will eliminate package resonance between the RF
input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
Notes: 1: Both RF ports must be held at 0 V
DC
or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 kΩresistor to V
DD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to V
SS
(-VDD) to bypass and
disable internal negative voltage generator.
4. Place a 10 kΩresistor in series, as close to pin as possible
to avoid frequency resonance. See “Resistor on Pin 1 & 3”
paragraph
Document No. 70-0160-04
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