PE64904
Product Specification
Figure 3. Pin Configuration (Top View)
Table 4. Absolute Maximum Ratings
Symbol
V
DD
V
I
V
ESD
Parameter/Conditions
Power supply voltage
Voltage on any DC input
ESD Voltage (HBM, MIL_STD
883 Method 3015.7)
Min
-0.3
-0.3
Max
4.0
4.0
1500
Units
V
V
V
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted
to the limits in the Operating Ranges table.
Operation between operating range maximum and
absolute maximum for extended periods may reduce
reliability.
Table 2. Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
Pin Name
RF-
RF-
DGND
V
DD
SCL
SEN
SDA
RF+
RF+
GND
Description
Negative RF Port
1
Negative RF Port
1
Ground
Power supply pin
Serial interface Clock input
Serial Interface Latch Enable Input
Serial interface Data input
Positive RF Port
1
Positive RF Port
1
RF Ground
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS
®
device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
®
devices are immune to latch-up.
Moisture Sensitivity Level
Note 1: Pins 1-2 and 8-9 must be tied together on PCB for optimal performance.
Table 3. Operating Ranges
Parameter
V
DD
Supply Voltage
I
DD
Power Supply Current (V
DD
= 2.6V)
I
DD
Standby Current (V
DD
= 2.6V)
V
IH
Control Voltage High
V
IL
Control Voltage Low
RF Input Power (50Ω)
1
Min
2.3
Typ
2.6
140
25
Max
3.6
200
3.6
0.57
+34
+32
30
30
30
Units
V
µA
µA
V
V
dBm
dBm
Vpk
Vpk
Vpk
°C
°C
The Moisture Sensitivity Level rating for the
PE64904 in the 10-lead 2 x 2 x 0.45 mm QFN
package is MSL1.
1.2
0
698 - 915 MHz
1710 -1910 MHz
1.8
0
Peak Operating RF Voltage
2
V
P
to V
M
V
P
to RFGND
V
M
to RFGND
T
OP
Operating Temperature Range
T
ST
Storage Temperature Range
-40
-65
+85
+150
Notes: 1. Maximum Power Available from 50Ω Source. Pulsed RF input with
4620 µS period, 50% duty cycle, measured per 3GPP TS 45.005.
2. Node voltages defined per Equivalent Circuit Model Schematic
(Figure
18).
When DTC is used as a part of reactive network, impedance
transformation may cause the internal RF voltages (V
P
, V
M
) to exceed Peak
Operating RF Voltage even with specified RF Input Power Levels. For
operation above about +20 dBm (100 mW), the complete RF circuit must
be simulated using actual input power and load conditions, and internal
node voltages (V
P
, V
M
in
Figure 18)
monitored to not exceed 30 Vpk.
Document No. 70-0325-06
│
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©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
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