PE83511
Product Specification
Figure 3. Pin Configuration (Top View)
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
V
DD
1
8
8
7
GND
IN
2
OUT
PE83511
N/C
3
4
6
5
CTL
GND
OUT
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 2. Pin Descriptions
Pin
No.
1
2
3
4
Pin
Name
V
DD
IN
N/C
GND
Device Functional Considerations
Description
Power supply pin. Bypassing is required
(eg 1000 pF & 100 pF).
Input signal pin. Should be coupled with a
capacitor (eg 1000 pF).
No connection. This pin should be left open.
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
Inverted divided frequency output. This pin
should be coupled with a capacitor
(eg 1000 pF).
Control pin. When grounded OUTB is
enabled.
Divided frequency output. This pin should
be coupled with a capacitor (eg 1000 pF).
Ground Pin.
The
PE83511
divides an input signal, up to a
frequency of 1500 MHz, by a factor of two thereby
producing an output frequency at half the input
frequency. To work properly at higher frequency,
the input and output signals (pins 2, 7 & optional
5) must be AC coupled via an external capacitor.
The input may be DC coupled for low frequency
operation with care taken to remain within the
specified DC input range for the device.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 8 for a layout example.
OUTB Control
Pin 6 controls whether OUTB is enabled or
disabled. Pin 6 has an internal pull-up resistor.
With no connection (floating), OUTB is disabled.
By grounding pin 6, OUTB is enabled. By
enabling OUTB, this part will consume roughly
5 mA more current.
5
OUTB
6
7
8
CTL
OUT
GND
Table 3. Absolute Maximum Ratings
Symbol
VDD
P
in
V
IN
T
ST
T
OP
VESD
Parameter/Conditions
Supply voltage
Input Power
Voltage on input
Storage temperature range
Operating temperature
range
ESD voltage (Human Body
Model, MIL-STD 883)
Min
Max
4.0
15
VDD
+0.3
150
125
2000
Units
V
dBm
V
°C
°C
V
-0.3
-65
-55
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage. Exposure
to absolute maximum ratings for extended periods
may affect device reliability.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 7
Document No. 70-0113-03
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UltraCMOS™ RFIC Solutions
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