PE9304
Preliminary Specification
Figure 7. Evaluation Board Schematic Diagram
J2-9
Figure 8. Evaluation Board Layout
C10
1000 pF
C2
100 pF
1
VDD
GND
8
2
IN
OUT
7
J1
2.2pF
C4
1000pF
C6
10nF
C3
1000 pF
3
C1
1000 pF
NC
NC
6
J3
2.2pF
4
GND
GND
5
J4
J5
Evaluation Kit Operation
The Ceramic SOIC Prescaler Evaluation Board was
designed to help customers evaluate the
PE9304
divide-by-2 prescaler. On this board, the device
input (pin 2) is connected to the SMA connector J1
through a 50
Ω
transmission line. A series
capacitor (C3) provides the necessary DC block for
the device input. A value of 2.2pF was used for the
evaluation board; other applications may require a
different value.
The device output (pin 7) is connected to SMA
connector J3 through a 50
Ω
transmission line. A
series capacitor (C1) provides the necessary DC
block for the device output. This capacitor value
must be chosen to have low impedance at the
desired output frequency of the device. A value of
2.2pF was chosen for the evaluation board.
J2 provides DC power to the device via pin 1. Two
decoupling capacitors (C2=1000pF, C10=100pF)
are included on this trace. It is the responsibility of
the customer to determine proper supply decoupling
for their design application.
The board is constructed using 4 layers. The top
and bottom layers are comprised of Rogers low loss
4350 material having a core thickness of 0.010”;
while the internal layers are comprised of FR-4.
The overall board thickness is 0.062”.
Applications Support
If you have a problem with your evaluation kit or if
you have applications questions call (858) 455-0660
and ask for applications support. You may also
contact us by fax or e-mail:
Fax:
(858) 455-0770
E-Mail:
help@peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0152~00A
|
UTSi
CMOS RFIC SOLUTIONS
Page 4 of 6
PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
