PI3A3159
3.0V, SOTiny
™
0.4Ω
SPDT Analog Switch
Test Circuits/Timing Diagrams
V
CC
V
CC
V
COM
NC
NO
RL
50Ω
Logic
Input
CL
35pF
VNO
VOUT
RL
50Ω
CL
35pF
Logic VINH
Input
VINL
Switch
Output
50%
tr <20ns
tf <20ns
tOFF
VOUT
0V
90%
90%
GND
tON
CL INCLUDES FIXTURE AND STRAY CAPACITANCE
RL
VOUT = VNO
R L + R ON
(
)
LOGIC INPUT WAVEFORMS INVERTED FOR
SWITCHES THAT HAVE OPPOSITE LOGIC
* 1.5V FOR 3.3V SUPPLY
Figure 1. Switching Time
V
CC
V
CC
V
OUT
IN
OFF
∆V
OUT
V
GEN
NO or
NC
.1µF
IN
Logic
Input
COM
C
L
1nF
V
OUT
ON
ON
Q = (∆V
OUT
)(C
L
)
OFF
GND
IN
OFF
OFF
Figure 2. Charge Injection
10nF
+3.3V
V
CC
10nF
V
CC
COM1
50Ω
Analyzer
IN
NC or
NO
50Ω
GND
0V to 2.4V
or
0V to 2V
Signal
Generator
0dBm
NC
NO
IN
Analyzer
V
CC
COM
50Ω
GND
50Ω
Figure 3. Off Isolation
Figure 4. Crosstalk
6
PS8710A
06/27/04
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
