PI49FCT3807
3.3V Fast CMOS Clock Driver
Tests Circuits for All Outputs
(1)
V
DD
Switch Position
Test
Disable LOW
Enable LOW
Switch
6V
GND
Open
Pulse
Generator
V
IN
V
OUT
D.U.T.
R
T
Disable HIGH
Enable HIGH
All Other Inputs
C
L
Definitions:
1. C
L
= Load capacitance: includes jig and
probe capacitance.
2. R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
Switching Waveforms
Propagation Delay
3V
Input
t
PLH
Output
t
R
t
PHL
1.5V
0V
V
OH
1.5V
V
OL
t
SK(p)
=
t
PHL
– t
PLH
Output
Pulse Skew – t
SK
(p)
3V
Input
t
PLH
t
PHL
1.5V
0V
V
OH
1.5V
V
OL
2.0V
0.5V
t
F
Output Skew – t
SK
(o)
3V
Input
t
PLHx
Ox
t
SK(o)
Oy
t
PLHy
t
PHLy
t
SK(o)
t
PHLx
1.5V
0V
V
OH
1.5V
V
OL
V
OH
1.5V
V
OL
Package Skew – t
SK
(t)
3V
Input
t
PLH1
Package 1
Output
t
SK(t)
Package 2
Output
t
PLH2
t
PHL2
t
SK(t)
t
PHL1
1.5V
0V
V
OH
1.5V
V
OL
V
OH
1.5V
V
OL
t
SK(o)
=
t
PLHy
– t
PLHx
or
t
PHLy
– t
PHLx
t
SK(t)
=
t
PLH2
– t
PLH1
or
t
PHL2
– t
PHL1
4
PS7010D
09/08/04
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
