PI49FCT20807
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1-10 Clock Buffer for
Networking Applications
Features
• High Frequency >150 MHz
• High-speed, low-noise, non-inverting 1-10 buffer
• Low-skew (<150ps) between any two output clocks
• Low duty cycle distortion <300ps
• Low propagation delay <3.5ns
• Multiple V
DD
, GND pins for noise reduction
• 2.5V supply voltage and 3V tolerant input
• Packaging (Pb-free & Green available):
-20-pin SOIC (S)
-20-pin SSOP (H)
-20-pin QSOP (Q)
Description
The PI49FCT20807, a 2.5V compatible, high-speed, low-noise 1-10
non-inverting clock buffer, is designed to target networking appli-
cations that require low-skew, low-jitter, and high-frequency clock
distribution. Providing output-to-output skew as low as 150ps, the
PI49FCT20807 is an ideal clock distribution device for synchronous
systems. Designing synchronous networking systems requires a
tight level of skew from a large number of outputs.
Pin Description
Pin Name
BUF_IN
CLK [0:9]
GND
V
DD
Input
Outputs
Ground
Power
De s cription
Block Diagram
CLK0
Pin Configuration
BUF_IN
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
VDD
CLK9
CLK8
GND
CLK7
VDD
CLK6
GND
CLK5
CLK4
CLK1
BUF_IN
CLK2
CLK0
VDD
CLK1
GND
20-Pin
H, Q, S
16
15
14
13
12
11
CLK3
CLK2
VDD
CLK3
CLK9
GND
1
PS8558B
09/24/04
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
