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PI6C102
Precision Clock Synthesizer
for Mobile PCs
Features
Two copies of CPU clock with V
DD
of 2.5V ±5%
100 MHz or 66.6 MHz operation
Six copies of PCI clock, (synchronous with CPU clock) 3.3V
One copy of Ref. Clock @ 14.31818 MHz (3.3V
TTL
)
Low cost 14.31818 MHz crystal oscillator input
Power management control
Isolated core V
DD
, V
SS
pins for noise reduction
28-pin SSOP package (H)
Description
The PI6C102 is a high-speed low-noise clock generator designed
to work with the Pericom's PI6C18x clock buffer to meet all clock
needs for Mobile Intel Architecture platforms. CPU and chipset
clock frequencies of 66.6 MHz and 100 MHz are supported.
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers a portion of the I/O and the core. The 2.5V is used to power
the remaining outputs. 2.5V signaling follows JEDEC standard 8-X.
Power sequencing of the 3.3V and 2.5V supplies is not required.
An asynchronous PWRDWN# signal may be used to orderly power
down (or up) the system.
Block Diagram
Pin Configuration
XTAL_IN
XTAL_OUT
REF
V
DDCPU
*KBBAHI
XTAL_IN
XTAL_OUT
PWRDWN#
SEL
SEL100/66#
2
CPUCLK
[0:1]
V
DDREF
REF
OSC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-Pin
H
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSSREF
VDDREF
REF
VDDCPU
CPUCLK0
CPUCLK1
VSSCPU
VDDCORE1
VSSCORE1
PCISTOP#
CPUSTOP#
PWRDWN#
SEL
SEL100/66#
VSSPCI0
PCICLK_F
PCICLK1
VDDPCI0
PCICLK2
PCICLK3
VDDPCI1
PCICLK4
PCICLK5
VSSPCI1
VDDCORE0
VSSCORE0
PLL1
DIV
CPUSTOP#
V
DDCPU
0,1
PCISTOP#
5
PCICLK
[1:5]
PCICLK_F
1
PS8164A
09/29/00
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
