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PI6C103
Precision Clock Synthesizer
for Mobile PCs
Features
Two copies of CPU clock
100 MHz or 66.6 MHz operation
Six copies of PCI clock, (synchronous with CPU clock)
Two copies of REF clock @ 14.31818 MHz
One copy of 48 MHz
One copy of selectable 48/24 MHz
Power management control input pins
Isolated core V
DD
, V
SS
pins for noise reduction
28-pin SSOP (H) and TSSOP (L) packages
SSC Options:
Device
PI6C103
PI6C103-05
PI6C103-06
66 MHz
0.67%
1.35%
1.79%
100 MHz
0.65%
1.35%
1.79%
Description
The PI6C103 is a high-speed, low-noise clock generator designed
to work with the PI6C18X clock buffer to meet all clock needs
for Mobile Intel Architecture platforms. System clock frequencies
of 66.6 MHz and 100 MHz are supported.
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers everything except the CPU clock. The 2.5V power supply is
used to power the CPUCLK outputs. 2.5V signaling follows JEDEC
standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is
not required.
An asynchronous PWR_DWN# signal may be used to orderly
power down (or up) the system. CPU and PCI clocks may also be
stopped by the CPU_STOP# and PCI_STOP# signals.
The PI6C103 contains the Spread Spectrum function for only those
clocks that synchronize to the CPU clocks (CPU and PCI clocks).
Block Diagram
XTAL_IN
XTAL_OUT
REF
OSC
2
Pin Configuration
REF
[0:1]
V
SS
XTAL_IN
XTAL_OUT
PCICLK_F
PCICLK1
PCICLK2
V
SS
V
DD
PCICLK3
PCICLK4
PCICLK5
V
DD
48 MHz
48-24MHz/TS#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
REF1/SEL48#
REF0/Spread#
V
DD
2
CPUCLK0
CPUCLK1
V
SS
2
V
SS
PCI_STOP#
V
DD
CPU_STOP#
PWR_DWN#
SEL100/66#
V
SS
SPREAD#
SEL100/66#
PLL1
DIV
CPU_STOP#
2
CPUCLK
[0:1]
PCICLK
[1:5]
PCICLK_F
5
PCI_STOP#
28-Pin
H, L
PWR_DWN#
TS#
48 MHz
PLL2
÷2
SEL48#
MUX
48/24 MHz
222
PS8315-2
04/08/99
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
