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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2509-133
Low-Noise, Phase-Locked Loop
Clock Driver with 9 Clock Outputs
Functional Table
Input Control
X
(1)
G
L
H
Outputs
X
(1)
Y[0:3]
L
CLK _IN
FB_O UT
CLK _IN
CLK _IN
Note:
1. X is either 1 or 2
Pin Functions
Pin Name
CLK_IN
FB_IN
1G
2G
FB_OUT
1Y[0:4]
2Y[3:0]
Pin No.
24
13
11
14
12
3,4,5,8,9
16,17,
20, 21
23
1
2,10,15,22
6,7,18,19
Type
I
I
I
I
O
O
O
De s cription
Clock input. CLK_IN allows spread spectrum.
Feedback input. FB_IN provides the feedback signal to the internal PLL.
Output bank enable. When 1G is LOW, outputs 1Y[0:4] are disabled to
a logic low state. When 1G is HIGH, all outputs 1Y[0:4] are enabled.
Output bank enable. When 2G is LOW, outputs 2Y[0:3] are disabled to
a logic low state. When 2G is HIGH, all outputs 2Y[0:3] are enabled.
Feedback output. FB_OUT is dedicated for external feedback. FB_OUT has an
embedded series- damping resistor of the same value as the clock outputs 1Yx, 2Yx.
Clock outputs. These outputs provide low- skew copies of CLK_IN.
Each output has an embedded series- damping resistor.
Clock outputs. These outputs provide low- skew copies of CLK_IN.
Each output has an embedded series- damping resistor.
Analog power supply. AV
CC
can be also used to bypass the PLL for
test purposes. When AV
CC
is strapped to ground, PLL is bypassed and CLK_IN.
is buffered directly to the device outputs.
Analog ground. AGND provides the ground reference for the analog circuitry.
Power supply.
Ground.
AV
CC
AGND
V
CC
GND
Power
Ground
Power
Ground
2
PSXXXX
06/01/99
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
