PI6C21200
1:12 Clock Driver for Intel PCI-Express Chipsets
Features
• Twelve Pairs of PCI-Express Differential Clocks (HCSL
compatible signaling)
• Low skew < 50ps
• Low jitter < 50ps
• Output Enable for all outputs
• Outputs tristate control via SMBus
• Power Management Control
• Programmable PLL Bandwidth
• PLL or Fan out operation
• Gear Ratio supporting different output frequencies
• 3.3V Operation
• 56-pin Packages (Pb-Free & Green):
- TSSOP (A56) and SSOP (V56)
Description
PI6C21200 is a high-speed, low-noise PCI-Express differential
clock buffer designed to be a companion with PI6C410B clock
synthesizer. The device distributes twelve copies of the
differential SRC clock coming from PI6C410B. The output
frequency can be ratioed to offer a derivative frequency from
the input frequency. Each differential output is controlled by
individual OE pin, except OUT10 and OUT11 are sharing one
OE_10#_11# pin. The clock outputs are controlled by input selec-
tion of SA_0, SA_1, SA_2 via SMBus, SCLK and SDA.
Block Diagram
OE [0:10]#
VTT_PWRGD#
/ PWRDWN
SCLK
SDA
SA_[0:1]
SA_2 /
PLLBypress#
SRC
SCR#
Pinout Diagram
Output
Control
HIGH_BW#
SRC_IN
SRC_IN#
SA_0
OE_0#
OUT0
OUT0#
OE_1#
OUT1
OUT1#
VDD
VSS
OUT2
OUT2#
OE_2#
OUT3
OUT3#
OE_3#
OUT4
OUT4#
OE_4#
VDD
VSS
OUT5
OUT5#
OE_5#
SA_1
SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_A
VSS_A
IREF
OE_10#_11#
OUT11
OUT11#
VDD
VSS
OUT10
OUT10#
FS_A
VTT_PWRGD# / PWRDWN
OE_9#
OUT9
OUT9#
OE_8#
OUT8
OUT8#
VDD
VSS
OUT7
OUT7#
OE_7#
OUT6
OUT6#
OE_6#
SA_2 /PLLBypass#
SCL
OUT0
OUT0#
OUT1
OUT1#
OUT2
OUT2#
OUT3
OUT3#
OUT4
OUT4#
OUT5
OUT5#
OUT6
OUT6#
SMBus
Controller
HIGH_BW#
PLL
OUT7
OUT7#
OUT8
OUT8#
OUT9
OUT9#
OUT10
OUT10#
OUT11
OUT11#
1
PS8820
02/28/06
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
