PI6C2510-133E
Low-Noise, Phase-Locked Loop
Clock Driver with 10 Clock Outputs
Features
• Operating Frequency up to 150 MHz
• Low-Noise Phase-Locked Loop Clock Distribution that
meets 133 MHz Registered DIMM Synchronous DRAM mod-
ules for server/workstation/PC applications
• Allows Clock Input to have Spread Spectrum modulation
for EMI reduction
• Low jitter: Cycle-to-Cycle jitter ±75ps max.
• On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
• Operates at 3.3V VCC, 0–85°C
• Packages (Pb-free & Green available):
– Plastic 24-pin TSSOP (L)
Description
The PI6C2510-133E is a “enhanced,” low-skew, low-jitter,
phase-locked loop (PLL) clock driver, distributing high-
frequency clock signals for SDRAM and server applications. By
connecting the feedback FB_OUT output to the feedback FB_IN
input, the propagation delay from the CLK_IN input to any
clock output will be nearly zero. This zero-delay feature allows
the CLK_IN input clock to be distributed, providing one clock
input to one bank of ten outputs, with an output enable.
This clock driver is designed to meet the PC133 SDRAM
Registered DIMM specification. For test purposes, the PLL can
be bypassed by strapping AVCC to ground.
Block Diagram
Pin Configuration
G
10
Y[0:9]
CLK_IN
PLL
FB_IN
AVcc
FB_OUT
AGND
V
CC
Y0
Y1
Y2
GND
GND
Y3
Y4
V
CC
G
FB_OUT
1
2
3
4
5
24-Pin
6
L
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK_IN
AV
CC
V
CC
Y9
Y8
GND
GND
Y7
Y6
Y5
V
CC
FB_IN
Functional Table
Inputs
G
L
H
Outputs
Y[0:9]
L
CLK_IN
FB_OUT
CLK_IN
CLK_IN
07-0199
1
PS8505B
08/30/07
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
