PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
Features
• PLL clock distribution optimized for DDR2 SDRAM
applications.
• Distributes one differential clock input pair to ten differential
clock output pairs.
• Differential Inputs (CLK, CLK) and (FBIN, FBIN)
• Input OE/OS: LVCMOS
• Differential Outputs (Y[0:9], Y[0:9] and (FBOUT, FBOUT)
• External feedback pins (FBIN, FBIN) are used to
synchronize the outputs to the clock input.
• Operates at AV
DD
= 1.8V for core circuit and internal PLL,
and V
DDQ
= 1.8V for differential output drivers
• Packaging (Pb-free & Green available):
– 52-ball VFBGA (NF)
Description
PI6CU877 PLL clock driver is developed for Registered DDR2
DIMM applications with 1.8V operation and differential data input
and output levels.
The device is a zero delay buffer that distributes a differential
clock input pair (CLK, CLK) to eleven differential pairs of clock
outputs which includes feedback clock (Y[0:9], Y[0:9]; FBOUT,
FBOUT).
The clock outputs are controlled by CLK/CLK, FBOUT, FBOUT, the
LVCMOS (OE, OS) and the Analog Power input (AV
DD
). When
OE is LOW the outputs except FBOUT, FBOUT, are disabled while
the internal PLL continues to maintain its locked-in frequency.
OS is a program pin that must be tied to GND or V
DD.
When OS
is high, OE will function as described above. When OS is LOW,
OE has no effect on Y7/Y7, they are free running. When AV
DD
is
grounded, the PLL is turned off and bypassed for test purposes.
When CLK/CLK are logic low, the device will enter a low power
mode. An input logic detection circuit will detect the logic low level
and perform a low power state where all Y[0:9], Y[0:9]; FBOUT,
FBOUT, and PLL are OFF.
3
Y
0
GND
NB
V
DDQ
NB
NB
V
DDQ
NB
GND
Y
4
Pin Configuration
1
A
B
C
D
E
F
G
H
J
k
Y
1
Y
1
Y
2
Y
2
CK
CK
AGND
AV
DD
Y
3
Y
3
2
Y
0
GND
GND
V
DDQ
V
DDQ
V
DDQ
V
DDQ
GND
GND
Y
4
4
Y
5
GND
NB
V
DDQ
NB
NB
V
DDQ
NB
GND
Y
9
5
Y
5
GND
GND
OS
V
DDQ
OE
V
DDQ
GND
GND
Y
9
6
Y
6
Y
6
Y
7
Y
7
FB
IN
FB
IN
FB
OUT
FB
OUT
Y
8
Y
8
PI6CU877 is a high performance, low skew, and low jitter PLL
clock driver, and it is also able to track Spread Spectrum Clocking
(SSC) for reduced EMI.
1
PS8689B
08/05/04
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
