PI6CV855L 参数 Datasheet PDF下载

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PI6CV855

PLL Clock Driver for 2.5V

SSTL 2 DDR SDRAM Memory

DC Specifications

Symbol

AV

DD

V

DDQ

V

OH

V

OL

V

IX

V

OX

V

IN

V

ID

V

OD

T

A

Recommended Operating Conditions

Parame te r

Analog/core supply voltage

O utput supply voltage

High- level output voltage

Low- level output voltage

Input differential- pair crossing voltage

O utput differential- pair crossing voltage at the SDRAM clock input

Input voltage level

Input differential voltage between CLK and CLK

O utput differential voltage between Y[n] and Y[n] and FBO UT

and FBO UT

O perating free air temperature

M in.

2.3

2.3

1.8

0

(V

DDQ

/2) –0.2

(V

DDQ

/2) –0.2

–0.3

0.36

0.7

0

Nom.

2.5

2.5

M ax.

2.7

2.7

V

DDQ

0.5

(V

DDQ

/2) +0.2

(V

DDQ

/2) +0.2

V

DDQ

+0.3

V

DDQ

+0.6

V

DDQ

+0.6

70

°C

V

Units

Electrical Characteristics

Parame te r

V

IK

I

I

I

DDQ

All inputs

CLK, FBIN

Dynamic supply current of V

DDQ

Static supply current

I

ADD

Dynamic supply current of AV

DD

Static supply current

CLK and CLK

FBIN and FBIN

Te s t Conditions

I

I

= –18mA

V

I

= V

DDQ

or GND

V

DD

= 2.7V

(1)

CLK & CLK <20 MHz

V

DD

= 2.7V

(1)

CLK & CLK <20 MHz

V

I

= V

DD

or GND

2.5V

2.0

A

VDD

, V

DDQ

2.3V

2.7V

M in.

Typ.

M ax.

–1.2

±10

300

100

12

100

3.0

Units

V

µA

mA

µA

mA

µA

pF

C

I

Notes:

1. Driving 9 or 18 DDR SDRAM memory chips with 120-ohm termination resistor for each clock output pair at 134 MHz.

2. The maximum power down clock frequency is below 20 MHz.

4

PS8545

06/20/01