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PI6CV857L
PLL Clock Driver for
2.5V DDR-SDRAM Memory
Product Features
PLL clock distribution optimized for Double Data Rate
SDRAM applications.
Distributes one differential clock input pair to ten differential
clock output pairs.
Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
Input PWRDWN: LVCMOS
Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the clock input.
Operates at AV
DD
= 2.5V for core circuit and internal PLL,
and V
DDQ
= 2.5V for differential output drivers
Available Packages: Plastic 48-pin TSSOP
Product Description
PI6CV857L PLL clock device is developed for registered DDR DIMM
applications This PLL Clock Buffer is designed for 2.5 V
DDQ
and 2.5V
AV
DD
operation and differential data input and output levels.
Package options include plastic Thin Shrink Small-Outline Package
(TSSOP).The device is a zero delay buffer that distributes a differ-
ential clock input pair (CLK, CLK) to ten differential pairs of clock
outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock
outputs (FBOUT,FBOUT) . The clock outputs are controlled by the
input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V
LVCMOS input (PWRDWN) and the Analog Power input (AV
DD
).
When input PWRDWN is low while power is applied, the input
receivers are disabled, the PLL is turned off and the differential clock
outputs are 3-stated. When the AV
DD
is strapped low, the PLL is
turned off and bypassed for test purposes.
When the input frequency falls below a suggested detection fre-
quency that is below the operating frequency of the PLL, the device
will enter a low power mode. An input frequency detection circuit will
detect the low frequency condition and perform the same low power
features as when the PWRDWN input is low.
The PLL in the PI6CV857L clock driver uses the input clocks (CLK,
CLK) and the feedback clocks (FBIN,FBIN) to provide high-perfor-
mance, low-skew, low-jitter output differential clocks (Y[0:9], Y[0:9]).
The PI6CV857L is also able to track Spread Spectrum Clocking for
reduced EMI.
Y0
Block Diagram/Pin Configuration
Y0
Y1
PLL
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Powerdown
and Test
Logic
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
CLK
CLK
FBIN
FBIN
PWRDWN
AVDD
GND
Y0
Y0
VD D Q
Y1
Y1
GND
GND
Y2
Y2
VD D Q
VD D Q
CLK
CLK
VD D Q
AV D D
AG N D
GND
Y3
Y3
VD D Q
Y4
Y4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-Pin
A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
Y5
Y5
VD D Q
Y6
Y6
GND
GND
Y7
Y7
VD D Q
P W R DW N
FBIN
FBIN
VD D Q
FBOUT
FBOUT
GND
Y8
Y8
VD D Q
Y9
Y9
GND
1
PS8543
06/11/01
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
