21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74STX1G79
SOTiny Gate STX Single Positive
Edge-Triggered D-Type Flip-Flop
AC Electrical Characteristics
T
A
= +25°C
Symbol
f
MAX
Parame te r
Maximum Clock Frequency
V
CC
(V)
1.8 ±0.15
2.5 ±0.2
3.3 ±0.3
5.0 ±0.5
1.8 ±0.15
2.5 ±0.2
3.3 ±0.3
5.0 ±0.5
3.3 ±0.3
5.0 ±0.5
t
S
Setup Time, CLK to D
IN
1.8 ±0.15
2.5 ±0.2
3.3 ±0.3
5.0 ±0.5
1.8 ±0.15
2.5 ±0.2
3.3 ±0.3
5.0 ±0.5
1.8 ±0.15
2.5 ±0.2
3.3 ±0.3
5.0 ±0.5
Conditions
C
L
= 50pF,
R
L
= 5
0
0 ohms
M in.
100
125
150
150
3.0
1.8
1.5
1.0
1.5
1.0
4.0
2.0
1.5
1.1
0.4
0.5
0.5
0.5
2.5
2.5
2.5
2.5
6.6
3.7
2.8
2.1
3.3
2.4
3.0
1.5
1.1
0.9
0
0
0
0
0.4
0.5
0.5
0.5
2.5
2.5
2.5
2.5
7.2
4.1
3.2
2.6
4.5
3.2
Typ.
M ax.
T
A
= 40°C to
+85°C
M in.
100
125
150
150
3.0
1.8
1.5
1.0
1.5
1.0
7.9
4.5
3.5
2.9
5.0
3.5
M ax.
Fig.
Units No.
MHz
1
3
t
PLH
,
t
PHL
Propagation Delay CLK to Q
OUT
C
L
= 15pF,
R
L
=
1
Mohm
C
L
= 50pF,
R
L
= 5
0
0 ohms
C
L
= 50pF,
R
L
= 5
0
0 ohms
1
3
1
3
1
4
ns
t
H
Hold Time, CLK to D
IN
C
L
= 50pF,
R
L
= 5
0
0 ohms
1
4
t
W
Pulse Width, CLK
C
L
= 50pF,
R
L
= 5
0
0 ohms
1
4
Capacitance
(3)
Symbol
C
IN
C
OUT
C
PD
Parame te r
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
(4)
Typ.
3
4
8
10
12
14
pF
M ax.
Units
Conditions
V
CC
= Open, V
IN
= 0V or V
CC
V
CC
= 3.3V, V
IN
= 0V or V
CC
V
CC
V
CC
V
CC
V
CC
=
=
=
=
1.8V
2.5V
3.3V
5.0V
Notes:
3. T
A
= +25°C, f= 1 MHz
4. C
PD
is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption
(I
CCD
) at no output loading and operating at 50% duty cycle (see Figure 2). C
PD
is related to I
CCD
dynamic operating current by
the expression: I
CCD
= (C
PD
)(V
CC
)(f
IN
) + (I
CC
static).
3
PS8569A
01/31/02
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
