PI7C21P100B
2-PORT PCI-X TO PCI-X BRIDGE
6.3
6.3.1
MODE AND CLOCK FREQUENCY DETERMINATION
PRIMARY BUS
PI7C21P100B does not have I/O pins for the M66EN or PCIXCAP signals on the primary
bus. PI7C21P100B adjusts its internal configuration based on the initialization pattern it
detects on P_DEVSEL#, P_STOP#, and P_TRDY# at the rising edge of P_RST#. If the
internal PLL is being used (the bus is configured in the PCI-X mode), a maximum of 100μs
from the rising edge of P_RST# is required to lock the PLL to the frequency of the clock
supplied on the P_CLK input.
6.3.2
SECONDARY BUS
The secondary interface is capable of operating in either conventional PCI mode or in PCI-X
mode. PI7C21P100B controls the mode and frequency for the secondary bus by utilizing a
pull-up circuit connected to S_PCIXCAP. There are two pull-up resistors in the circuit as
recommended by the PCI-X addendum. The first resistor is a weak pull-up (56K ohms)
whose value is selected to set the voltage of S_PCIXCAP below its low threshold when a
PCI-X 66 device is attached to the secondary bus. The second resistor is a strong pull-up,
externally wired between S_PCIXCAP and S_PCIXCAP_PU. The value of the resistor (1K
ohm) is selected to set the voltage of S_PCIXCAP above its high threshold when all devices
on the secondary are PCI-X 66 capable. To detect the mode and frequency of the secondary
bus, S_PCIXCAP_PU is initially disabled and PI7C21P100B samples the value on
S_PCIXCAP.
If PI7C21P100B sees a logic LOW on S_PCIXCAP, one or more devices on the secondary
have either pulled the signal to ground (PCI-X 66 capable) or tied it to ground (only capable
of conventional PCI mode). To differentiate between the two conditions, PI7C21P100B then
enables S_PCIXCAP_PU to put the strong pull-up into the circuit. If S_PCIXCAP remains at
a logic LOW, it must be tied to ground by one or more devices, and the bus is initialized to
conventional PCI mode. If S_PCIXCAP_PU can be pulled up, one or more devices are
capable of only PCI-X 66 operation so the bus is initialized to PCI-X 66 mode. If
PI7C21P100B sees a logic HIGH on S_PCIXCAP, then all devices on the secondary bus are
capable of PCI-X 133 operation. PI7C21P100B then samples S_SEL100 to distinguish
between the 66-100 MHz and the 100-133 MHz clock frequency ranges. If PI7C21P100B
sees logic HIGH on S_SEL100, the secondary bus is initialized to PCI-X 100 mode. If the
value is LOW, PCI-X 133 is initialized. These two ranges allow adjustment of the clock
frequency to account for bus loading conditions.
There is no pin for M66EN for the secondary interface on PI7C21P100B because the internal
PLL is bypassed in conventional PCI mode. S_CLK is used directly, eliminating the need to
distinguish between conventional PCI 33 and conventional PCI 66.
Page 36 of 79
November 2005 – Revision 1.02
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
