PI7C21P100B
2-PORT PCI-X TO PCI-X BRIDGE
BIT
22
21
20:16
FUNCTION
Reserved
66MHz Capable
Reserved
TYPE
RO
RO
RO
DESCRIPTION
Reserved.
Returns 0 when read.
66MHz Capable Status
1:
Capable of 66MHz operation
Returns 1 when read.
Reserved.
Returns 00000 when read.
8.1.21
MEMORY BASE REGISTER – OFFSET 20h
BIT
15:4
FUNCTION
Memory Base
TYPE
RW
DESCRIPTION
Specifies the base of the memory mapped I/O address range
bit[31:20] and is used with the Memory Limit register to specify a
range of 32-bit addresses supported for memory mapped I/O
transactions.
Reset to 800h
Reserved. Returns 0 when read
3:0
Reserved
RO
8.1.22
MEMORY LIMIT REGISTER – OFFSET 20h
BIT
31:20
19:16
FUNCTION
Memory Limit
Reserved
TYPE
RW
RO
DESCRIPTION
Specifies address bits[31:20] of the limit address for the address
range of memory mapped I/O operations.
Reset to 000h
Reserved. Returns 0 when read
8.1.23
PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h
BIT
15:4
3:0
FUNCTION
Prefetchable Memory
Base
64-bit Addressing
TYPE
RW
RO
DESCRIPTION
Specifies address bits[31:20] of the base address for the address
range of prefetchable memory operations.
Reset to 800h
Designates 64-bit addressing support. Returns 1h when read.
8.1.24
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h
BIT
31:20
19:16
FUNCTION
Prefetchable Memory
Limit
64-bit Addressing
TYPE
RW
RO
DESCRIPTION
Specifies address bits[31:20] of the limit address for the address
range of prefetchable memory operations.
Reset to 800h
Designates 64-bit addressing support. Returns 1h when read.
8.1.25
PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h
BIT
31:0
FUNCTION
Prefetchable Base
Upper 32-bit
TYPE
RW
DESCRIPTION
Specifies address bits[63:32] of the base address for the address
range of prefetchable memory operations.
Reset to 0000 0000h
Page 48 of 79
November 2005 – Revision 1.02
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
