PI7C21P100B
2-PORT PCI-X TO PCI-X BRIDGE
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DESCRIPTION
The PI7C21P100B is a 2-port PCI-X 2.0 Bridge designed to be compliant with the
PCI-X
Addendum to the Local Bus Specification
Revision 1.0a. The PI7C21P100B is able to handle
64-bit data at a maximum bus frequency of 133MHz. The PI7C21P100B is designed for high
speed applications such as Ethernet, SCSI, and Fibre Channel. The PI7C21P100B may also
be used for bus expansion, frequency isolations/translations, or PCI-X to PCI
isolations/translations.
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FEATURES
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INDUSTRY STANDARDS COMPLIANCE
PCI-X Addendum to the Local Bus Specification
Revision 1.0a (Mode 1 only)
PCI Local Bus Specification
Revision 2.2
PCI-to-PCI Bridge Architecture Specification
Revision 1.1
PCI Power Management Interface Specification
Revision 1.1
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Supports D0 and D3 power states
INTERFACE
3.3V signaling
133MHz / 64-bit operation on both buses
Dual address cycle support
Concurrent primary and secondary bus operation
Primary and secondary may be run in either PCI mode or PCI-X Mode 1
Asynchronous operation support
Programmable internal arbiter with support for up to 6 external masters on the
secondary bus
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Internal arbiter may be disabled to use an external arbiter
IEEE 1149.1 JTAG support
OPERATION
Type 0 and Type 1 configuration support
Configuration register access from both primary and secondary buses
2KB of buffering for upstream memory burst read commands
2KB of buffering for downstream memory burst read commands
1KB of buffering for upstream posted memory write commands
1KB of buffering for downstream posted memory write commands
Support for up to 8 active transactions in each direction
ADDITIONAL FEATURES
Capabilities pointer
Ability to define an opaque memory address
Definable base address register
Secondary side PCI-X device privatization
PACKAGING
304-pin PBGA, 31 x 31 mm
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Page 9 of 79
November 2005 – Revision 1.02
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
