ADVANCE INFORMATION
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PI7C7100
3-Port PCI Bridge
List of Figures
1-1.
1-2.
1-3.
2-1.
9-1.
15-1.
16-1.
17-1.
PI7C7100 on the System Board .................................................................................................................................... 2
PI7C7100 in Redundant Applications .......................................................................................................................... 2
PI7C7100 on Network Switching Hub .......................................................................................................................... 2
PI7C7100 Block Diagram .............................................................................................................................................. 3
Secondary Arbiter Example ....................................................................................................................................... 48
Test Access Port Block Diagram ............................................................................................................................... 72
PCI Signal Timing Measurement Conditions ............................................................................................................ 80
256-Pin PBGA Package Drawing ................................................................................................................................ 81
List of Tables
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
6-1.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
15-1.
15-2.
PCI Transaction ......................................................................................................................................................... 13
Write Transaction Forwarding .................................................................................................................................. 14
Write Transaction Disconnect Address Boundaries ................................................................................................ 16
Read Pre-fetch Address Boundaries ......................................................................................................................... 17
Read Transaction Pre-fetching .................................................................................................................................. 18
Device Number to IDSEL S1_AD or S2_AD Pin Mapping ....................................................................................... 21
Delayed Write Target Termination Response ........................................................................................................... 24
Responses to Posted Write Target Termination ....................................................................................................... 25
Responses to Delayed Read Target Termination ...................................................................................................... 25
Summary of Tranaction Ordering .............................................................................................................................. 33
Setting the Primary Interface Detected Parity Error Bit ............................................................................................. 39
Setting the Secondary Interface Detected Parity Error Bit ........................................................................................ 40
Setting the Primary Interface Data Parity Detected Bit .............................................................................................. 40
Setting the Secondary InterfaceData Parity Detected Bit ......................................................................................... 41
Assertion of P_PERR# ............................................................................................................................................... 42
Assertion of S_PERR# ............................................................................................................................................... 43
Assertion of P_SERR# for Data Parity Errors ........................................................................................................... 44
TAP Pins .................................................................................................................................................................... 73
JTAG Boundary Register Order ................................................................................................................................ 75
vii
09/18/00
Rev 1.1
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
