PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
2
2.1
SIGNAL DEFINITIONS
Signal Types
Signal Type
I
O
P
TS
STS
OD
Description
Input Only
Output Only
Power
Tri-State bi-directional
Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when
deasserting.
Open Drain
2.2
Signals
Note: Signal names that end with “_L” are active LOW.
2.2.1
PRIMARY BUS INTERFACE SIGNALS
Name
P_AD[31:0]
Pin #
49, 50, 55, 57, 58,
60, 61, 63, 67, 68,
70, 71, 73, 74, 76,
77, 93, 95, 96, 98,
99, 101, 107, 109,
112, 113, 115,
116, 118, 119,
121, 122
64, 79, 92, 110
Type
TS
Description
Primary Address / Data:
Multiplexed address and data
bus. Address is indicated by P_FRAME_L assertion.
Write data is stable and valid when P_IRDY_L is
asserted and read data is stable and valid when
P_TRDY_L is asserted. Data is transferred on rising
clock edges when both P_IRDY_L and P_TRDY_L are
asserted. During bus idle, PI7C8150 drives P_AD to a
valid logic level when P_GNT_L is asserted.
Primary Command/Byte Enables:
Multiplexed
command field and byte enable field. During address
phase, the initiator drives the transaction type on these
pins. After that, the initiator drives the byte enables
during data phases. During bus idle, PI7C8150 drives
P_CBE[3:0] to a valid logic level when P_GNT_L is
asserted.
Primary Parity.
Parity is even across P_AD[31:0],
P_CBE[3:0], and P_PAR (i.e. an even number of 1’s).
P_PAR is an input and is valid and stable one cycle after
the address phase (indicated by assertion of
P_FRAME_L) for address parity. For write data phases,
P_PAR is an input and is valid one clock after
P_IRDY_L is asserted. For read data phase, P_PAR is
an output and is valid one clock after P_TRDY_L is
asserted. Signal P_PAR is tri-stated one cycle after the
P_AD lines are tri-stated. During bus idle, PI7C8150
drives P_PAR to a valid logic level when P_GNT_L is
asserted.
Primary FRAME (Active LOW).
Driven by the
initiator of a transaction to indicate the beginning and
duration of an access. The de-assertion of P_FRAME_L
indicates the final data phase requested by the initiator.
Before being tri-stated, it is driven to a de-asserted state
for one cycle.
P_CBE[3:0]
TS
P_PAR
90
TS
P_FRAME_L
80
STS
2
August 22, 2002 – Revision 1.02
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
