PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
When PI7C8150A accepts a delayed read request, it first samples the read address, read bus
command, and address parity. When IRDY_L is asserted, PI7C8150A then samples the
byte enable bits for the first data phase. This information is entered into the delayed
transaction queue. PI7C8150A terminates the transaction by signaling a target retry to the
initiator. Upon reception of the target retry, the initiator is required to continue to repeat the
same read transaction until at least one data transfer is completed, or until a target response
(target abort or master abort) other than a target retry is received.
3.6.5
DELAYED READ COMPLETION WITH TARGET
When delayed read request reaches the head of the delayed transaction queue, PI7C8150A
arbitrates for the target bus and initiates the read transaction only if all previously queued
posted write transactions have been delivered. PI7C8150A uses the exact read address and
read command captured from the initiator during the initial delayed read request to initiate
the read transaction. If the read transaction is a non-prefetchable read, PI7C8150A drives
the captured byte enable bits during the next cycle. If the transaction is a prefetchable read
transaction, it drives all byte enable bits to zero for all data phases. If PI7C8150A receives
a target retry in response to the read transaction on the target bus, it continues to repeat the
read transaction until at least one data transfer is completed, or until an error condition is
encountered. If the transaction is terminated via normal master termination or target
disconnect after at least one data transfer has been completed, PI7C8150A does not initiate
any further attempts to read more data.
If PI7C8150A is unable to obtain read data from the target after 2
24
(default) or 2
32
(maximum) attempts, PI7C8150A will report system error. The number of attempts is
programmable. PI7C8150A also asserts P_SERR_L if the primary SERR_L enable bit is
set in the command register. See Section 6.4 for information on the assertion of
P_SERR_L.
Once PI7C8150A receives DEVSEL_L and TRDY_L from the target, it transfers the data
read to the opposite direction read data queue, pointing toward the opposite inter-face,
before terminating the transaction. For example, read data in response to a downstream
read transaction initiated on the primary bus is placed in the upstream read data queue. The
PI7C8150A can accept one DWORD of read data each PCI clock cycle; that is, no master
wait states are inserted. The number of DWORD’s transferred during a delayed read
transaction depends on the conditions given in Table 3-4 (assuming no disconnect is
received from the target).
3.6.6
DELAYED READ COMPLETION ON INITIATOR BUS
When the transaction has been completed on the target bus, and the delayed read data is at
the head of the read data queue, and all ordering constraints with posted write transactions
have been satisfied, the PI7C8150A transfers the data to the initiator when the initiator
repeats the transaction. For memory read transactions, PI7C8150A aliases the memory
read, memory read line, and memory read multiple bus commands when matching the bus
command of the transaction to the bus command in the delayed transaction queue.
PI7C8150A returns a target disconnect along with the transfer of the last DWORD of read
data to the initiator. If PI7C8150A initiator terminates the transaction before all read data
has been transferred, the remaining read data left in data buffers is discarded.
Page 29 of 111
APRIL 2006 – Revision 1.1
06-0057
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
