PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
The delayed transaction queue is full, and the transaction cannot be queued.
A delayed read request with the same address and bus command has already been
queued.
A locked sequence is being propagated across PI7C8150A, and the read transaction is
not a locked transaction.
PI7C78150B is currently discarding previously pre-fetched read data.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
For posted write transactions:
The posted write data buffer does not have enough space for address and at least one
DWORD of write data.
A locked sequence is being propagated across PI7C8150A, and the write transaction is
not a locked transaction.
When a target retry is returned to the initiator of a delayed transaction, the initiator
must repeat the transaction with the same address and bus command as well as the data
if it is a write transaction, within the time frame specified by the master timeout value.
Otherwise, the transaction is discarded from the buffers.
3.8.4.2
TARGET DISCONNECT
PI7C8150A returns a target disconnect to an initiator when one of the following conditions
is met:
PI7C8150A hits an internal address boundary.
PI7C8150A cannot accept any more write data.
PI7C8150A has no more read data to deliver.
See Section 3.5.4 for a description of write address boundaries, and Section 3.6.3 for a
description of read address boundaries.
3.8.4.3
TARGET ABORT
PI7C8150A returns a target abort to an initiator when one of the following conditions is
met:
PI7C8150A is returning a target abort from the intended target.
Page 40 of 111
APRIL 2006 – Revision 1.1
06-0057
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
