PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
If PI7C8150A detects that an initiator has failed to assert S_FRAME_L after 16 cycles of
both grant assertion and a secondary idle bus condition, the arbiter de-asserts the grant.
To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one
grant signal in the same PCI cycle in which it de-asserts another. It de-asserts one grant and
asserts the next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is
busy, that is, S_FRAME_L or S_IRDY_L is asserted, the arbiter can be de-asserted one
grant and asserted another grant during the same PCI clock cycle.
8.2.2
PREEMPTION
Preemption can be programmed to be either on or off, with the default to on (offset 4Ch, bit
31=0). Time-to-preempt can be programmed to 0, 1, 2, 4, 8, 16, 32, or 64 (default is 0)
clocks. If the current master occupies the bus and other masters are waiting, the current
master will be preempted by removing its grant (GNT#) after the next master waits for the
time-to-preempt.
8.2.3
SECONDARY BUS ARBITRATION USING AN EXTERNAL
ARBITER
The internal arbiter is disabled when the secondary bus central function control pin,
S_CFN_L, is tied HIGH. An external arbiter must then be used.
When S_CFN_L is tied HIGH, PI7C8150A, reconfigures two pins to be external request
and grant pins. The S_GNT_L[0] pin is reconfigured to be the external request pin because
it’s an output. The S_REQ_L[0] pin is reconfigured to be the external grant pin because
it’s an input. When an external arbiter is used, PI7C8150A uses the S_GNT_L[0] pin to
request the secondary bus. When the reconfigured S_REQ_L[0] pin is asserted LOW after
PI7C8150A has asserted S_GNT_L[0], PI7C8150A initiates a transaction on the secondary
bus one cycle later. If grant is asserted and PI7C8150A has not asserted the request,
PI7C8150A parks AD, CBE and PAR pins by driving them to valid logic levels.
The unused secondary bus grant outputs, S_GNT_L[8:1] are driven HIGH. The unused
secondary bus request inputs, S_REQ_L[8:1], should be pulled HIGH.
8.2.4
BUS PARKING
Bus parking refers to driving the AD[31:0], CBE[3:0], and PAR lines to a known value
while the bus is idle. In general, the device implementing the bus arbiter is responsible for
parking the bus or assigning another device to park the bus. A device parks the bus when
the bus is idle, its bus grant is asserted, and the device’s request is not asserted. The AD
and CBE signals should be driven first, with the PAR signal driven one cycle later.
PI7C8150A parks the primary bus only when P_GNT_L is asserted, P_REQ_L is de-
asserted, and the primary PCI bus is idle. When P_GNT_L is de-asserted, PI7C8150A 3-
states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If PI7C8150A is
parking the primary PCI bus and wants to initiate a transaction on that bus, then
Page 68 of 111
APRIL 2006 – Revision 1.1
06-0057
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
