PI90SD1636C
SERDES Gigabit Ethernet Transceiver
Features
• IEEE 802.3z Gigabit Ethernet Compliant
• Supports 1.25 Gbps Using NRZ Coding over uncompensated
twin coax cable
• Fully integrated CMOS IC
• Low Power Consumption
• ESD rating >2000V (Human Body Model) or > 200V (Ma-
chine Model)
• 5-Volt Input Tolerance
• Pin-Compatible with Agilent HDMP1636A/HDMP- 1646A
and Vitesse VSC7123 transceivers (see Appendix A)
• Packaging (Pb-free & Green available):
- 64-pin LQFP (FC)
- 64-pin LQFP (FD)
Description
The PI90SD1636C is a single chip, Gigabit Ethernet transceiver.
It performs all the functions of the Physical Medium Attachment
(PMA) portion of the Physical layer, as specified by the IEEE
802.3z Gigabit Ethernet standard. These functions include parallel-
to-serial and serial-to-parallel conversion, clock generation, clock
data recovery, and word synchronization. In addition, an internal
loopback function is provided for system debugging.
The PI90SD1636C is ideal for Gigabit Ethernet, serial backplane
and proprietary point-to-point applications. The device sup-
ports 1000BASE-LX and 1000BASE-SX
fi
ber-optic media, and
1000BASE-CX copper media.
The transmitter section of the PI90SD1636C accepts 10-bit wide
parallel TTL data and converts it to a high speed serial data stream.
The parallel data is encoded in 8b/10b format. This incoming
parallel data is latched into an input register, and synchronized
on the rising edge of the 125 MHz reference clock supplied by
the user. A phase locked loop (PLL) locks to the 125 MHz clock.
The clock is then multiplied by 10 to produce a 1.25 GHz serial
clock that is used to provide the high speed serial data output. The
output is sent through a Pseudo Emitter Coupled Logic (PECL)
driver. This output connects directly to a copper cable in the case
of 1000BASE-CX medium, or to a
fi
ber optic module in the case
of 1000BASE-LX or 1000BASE SX
fi
ber optic medium.
The receiver section of the PI90SD1636C accepts a serial PECL-
compatible data stream at a 1.25 Gbps rate, recovers the original
10-bit wide parallel data format, and retimes the data. A PLL locks
onto the incoming serial data stream, and recovers the 1.25 GHz
high speed serial clock and data. This is accomplished by con-
tinually frequency locking onto the 125 MHz reference clock, and
by phase locking onto the incoming data stream. The serial data
is converted back to parallel data format. The ‘comma’ character
is used to establish byte alignment. Two 62.5 MHz clocks, 180
degrees out of phase, are recovered. These clocks are alternately
used to clock out the parallel data on the rising edge. This parallel
data is sent to the user in TTL-compatible form.
Applications
•
•
•
•
Gigabit Ethernet
Serial Backplane
Proprietary point-to-point applicaitons
Passive Optical Networks
07-0253
1
PS8922A
11/08/07
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
