Linear Photodiode Array
Imagers
Figure 3: Transfer Timing Diagram
Horizontal Shift Registers
t
6
t
1
Charge packets collected in the photo-
diodes as light is received are converted
to a serialized output stream through a
buried-channel, two-phase CCD shift
register that provides high charge trans-
fer efficiency at shift frequencies up to
40 MHz. The PerkinElmer 5-volt CCD
process used in this design enables
low-power, high-speed operation
with inexpensive, readily available
driver devices.
Ø
PG
t
5
t
3
t
t
2
6
Ø
t
TG
4
t
t
Ø
8
7
AB
Ø
1
The transfer gate (ØTG) controls the
movement of charge packets from the
photodiodes to the CCD shift register.
During charge integration, the voltage
controlling the transfer gate is
V
Out
Note 1
Note 2
Notes:
1. Transition and dark pixels
2. Active pixels
held in its low state to isolate the
photodiodes from the shift register.
When transfer of charge to the shift
register is desired, øTG is switched to
its high state to create a transfer
channel between the photodiodes and
the shift register. The charge transfer
sequence, detailed in Figure 4, proceeds
as follows:
Table 1. Transfer Timing Requirements
Item
Sym
Min
Typ
Max
Delay of øTG falling edge from
øPG falling edge
t1
5 ns
20 ns
-
Delay of øTG rising edge from end
of ø1 and ø2 clocks
t2
t3
0 ns
5 ns
10 ns
5 ns
-
-
After readout of a particular image line
(n), the shift register is empty of charge
and ready to accept new charge packets
from the photodiodes representing
image line (n+1). To begin the transfer
sequence, the horizontal clock pulses
(ø1 and ø2) are stopped with ø1 held in
its high state, and ø2 in its low state.
The transfer gate voltage phase (øTG) is
then switched high to start the transfer
of charge to the shift register. Once the
transfer gate reaches its high state, the
photo gate voltage (øPG) is set high to
complete the transfer. It is recom-
mended that the photo gate voltage be
held in the high state for at least 0.1 µs
to ensure complete transfer. After this
interval, the photo gate voltage is
Delay of øAB rising edge from
øPG falling edge
øTG pulse width
øPG pulse width
Rise/fall time
t4
t5
t6
100 ns
100 ns
10 ns
500 ns
400 ns
-
-
-
20 ns
-
Integration time
øAB pulse width
t7
t8
0 ns
-
-
-
1
750 ns
Note 1: 750ns is the typical time to fully reset the photodiode.
Figure 4: Readout Timing Waveforms
t
1
t
2
returned to its low state, and when
that is completed, the transfer gate
voltage is also returned to the low
state. The details of the transfer timing
are shown in Figure 3 with ranges and
tolerances in Table 1.
Ø
1
Ø
2
t
6
t
5
t
4
After transfer, the charge is transported
along the shift register by the alternate
action of two horizontal phase voltages
Ø
RG
w w w . p e r k in e lm e r . c o m / o p t o
DSP-101 01H - 7/2002W Page 3
PERKINELMER [ PERKINELMER OPTOELECTRONICS ]
