Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
FEATURES
•
Complies with JEDEC standard no. 8-1A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns.
DESCRIPTION
The 74HC/HCT08 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A. The 74HC/HCT08 provide the 2-input
AND function.
TYPICAL
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. For 74HC08: the condition is V
I
= GND to V
CC
.
For 74HCT08: the condition is V
I
= GND to V
CC
−
1.5 V.
FUNCTION TABLE
INPUT
nA
L
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
nB
L
H
L
H
OUTPUT
nY
L
L
L
H
PARAMETER
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate
notes 1 and 2
CONDITIONS
74HC08
C
L
= 15 pF; V
CC
= 5 V
7
3.5
10
74HCT08
11
3.5
20
ns
pF
pF
UNIT
2003 Jul 25
2
PHILIPS [ NXP SEMICONDUCTORS ]
