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74HC138 参数 Datasheet PDF下载

74HC138图片预览
型号: 74HC138
PDF下载: 下载PDF文件 查看货源
内容描述: 3至8线译码器/多路分解器;反相 [3-to-8 line decoder/demultiplexer; inverting]
分类和应用:
文件页数/大小: 7 页 / 54 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
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Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
FEATURES
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT138 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
74HC/HCT138
The 74HC/HCT138 decoders accept three binary
weighted address inputs (A
0
, A
1
, A
2
) and when enabled,
provide 8 mutually exclusive active LOW outputs (Y
0
to
Y
7
).
The “138” features three enable inputs: two active LOW
(E
1
and E
2
) and one active HIGH (E
3
). Every output will be
HIGH unless E
1
and E
2
are LOW and E
3
is HIGH.
This multiple enable function allows easy parallel
expansion of the “138” to a 1-of-32 (5 lines to 32 lines)
decoder with just four “138” ICs and one inverter.
The ”138” can be used as an eight output demultiplexer by
using one of the active LOW enable inputs as the data
input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their
appropriate active HIGH or LOW state.
The ”138” is identical to the “238” but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
PARAMETER
propagation delay
t
PHL
/ t
PLH
t
PHL
/ t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
A
n
to Y
n
E
3
to Y
n
E
n
to Y
n
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
12
14
3.5
67
17
19
3.5
67
ns
ns
pF
pF
HCT
UNIT
September 1993
2