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NE5537N 参数 Datasheet PDF下载

NE5537N图片预览
型号: NE5537N
PDF下载: 下载PDF文件 查看货源
内容描述: 采样和保持放大器 [Sample-and-hold amplifier]
分类和应用: 采样保持电路放大器放大器电路光电二极管
文件页数/大小: 8 页 / 107 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
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Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifier
NE/SE5537
DESCRIPTION
The NE5537 monolithic sample-and-hold amplifier combines the
best features of ion-implanted JFETs with bipolar devices to obtain
high accuracy, fast acquisition time, and low droop rate. This device
is pin-compatible with the LF198, and features superior performance
in droop rate and output drive capability. The circuit shown in Figure
1 contains two operational amplifiers which function as a unity gain
amplifier in the sample mode. The first amplifier has bipolar input
transistors which give the system a low offset voltage. The second
amplifier has JFET input transistors to achieve low leakage current
from the hold capacitor. A unique circuit design for leakage current
cancellation using current mirrors gives the NE5537 a low droop
rate at higher temperature. The output stage has the capability to
drive a 2kΩ load. The logic input is compatible with TTL, PMOS or
CMOS logic. The differential logic threshold is 1.4V with the sample
mode occurring when the logic input is high. It is available in 8-lead
TO-5, 8-pin plastic DIP packages, and 14-pin SO packages.
PIN CONFIGURATIONS
FE and N Packages
V+ 1
OFFSET ADJUST 2
INPUT 3
V– 4
8
7
6
5
LOGIC
LOGIC REFERENCE
C
h
OUTPUT
D
1
Package
INPUT
NC
V–
NC
NC
1
2
3
4
5
6
7
14
V
OS
ADJ
13
NC
12
V+
11
LOGIC
10
LOGIC REFERENCE
9
8
NC
C
h
FEATURES
NC
OUTPUT
Operates from
±5V
to
±18V
supplies
Hold leakage current 6pA @ T
J
= 25°C
Less than 4µs acquisition time
TTL, PMOS, CMOS compatible logic input
0.5mV typical hold step at CH=0.01µF
Low input offset: 1MV (typical)
0.002% gain accuracy with R
L
=2kΩ
Low output noise in hold mode
Input characteristics do not change during hold mode
High supply rejection ratio in sample or hold
Wide bandwidth
NOTE:
1. SO and non-standard pinouts.
BLOCK DIAGRAM
OFFSET
2
30k
5
3
+
OUTPUT
INPUT
LOGIC
8
+
300
7
LOGIC
REFERENCE
6
HOLD
CAPACITOR
ORDERING INFORMATION
DESCRIPTION
8-Pin Plastic Dual In-Line Package (DIP)
14-Pin Plastic Small Outline (SO) Package
8-Pin Plastic Dual In-Line Package (DIP)
TEMPERATURE RANGE
0 to +70°C
0 to +70°C
-55°C to +125°C
ORDER CODE
NE5537N
NE5537D
SE5537FE
DWG #
0404B
0175D
0404B
August 31, 1994
884
853-1044 13721