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ADNS-3080 参数 Datasheet PDF下载

ADNS-3080图片预览
型号: ADNS-3080
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能光学鼠标传感器 [High-Performance Optical Mouse Sensor]
分类和应用: 传感器
文件页数/大小: 38 页 / 637 K
品牌: PIXART [ PIXART IMAGING INC. ]
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PixArt Imaging Inc.
High-Performance Optical Mouse Sensor
AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, V
DD3
=3.3V, fclk=24MHz.
Parameter
VDD to RESET
Data delay
after RESET
Input delay
after reset
Power Down
Wake from NPD
Symbol
t
OP
t
PU-RESET
T
IN-RST
t
PD
t
PUPD
Min.
Typical
Max.
250
35
500
2.1
75
Units
s
ms
s
ms
ms
Notes
From VDD = 3.0V to RESET sampled
From RESET falling edge to valid motion data at
2000 fps and shutter bound 8290.
From RESET falling edge to inputs active (NPD,
MOSI, NCS, SCLK)
From NPD falling edge to initiate the power down
cycle at 500fps (tpd = 1 frame period + 100ms )
From NPD rising edge to valid motion data at
2000 fps and shutter bound 8290. Max assumes
surface change while NPD is low.
From NPD rising edge to all registers contain data
from new images at 2000fps (see Figure 10) .
Data delay
after NPD
RESET pulse width
MISO rise time
MISO fall time
MISO delay
afterSCLK
MISO hold time
MOSI hold time
MOSI setup time
SPI time between
write commands
SPI time between
write and read
commands
t
COMPUTE
t
PW-RESET
t
r-MISO
t
f-MISO
t
DLY-MISO
t
hold-MISO
t
hold-MOSI
t
setup-MOSI
t
SWW
t
SWR
250
200
120
50
50
10
40
40
3.1
ms
s
200
200
120
ns
ns
ns
ns
ns
ns
s
s
C
L
= 50pF
C
L
= 50pF
From SCLK falling edge to MISO data valid, no
load conditions
Data held until next falling SCLK edge
Amount of time data is valid after SCLK rising
edge
From data valid to SCLK rising edge
From rising SCLK for last bit of the first data byte,
to rising SCLK for last bit of the second data byte.
From rising SCLK for last bit of the first data byte,
to rising SCLK for last bit of the second address
byte.
From rising SCLK for last bit of the first data byte,
to falling SCLK for first bit of the second address
byte.
From rising SCLK for last bit of the address byte,
to falling SCLK for first bit of data being read. All
registers except Motion & Motion_Burst
From rising SCLK for last bit of the address byte, to
falling SCLK for first bit of data being read. Applies
to 0x02 Motion, and 0x50 Motion_Burst, registers
From NCS falling edge to first SCLK rising edge
From last SCLK falling edge to NCS rising edge,
for valid MISO data transfer
From NCS rising edge to MISO high-Z state
(see Figure 23 and 24)
SPI time between
t
SRW
read and subsequent t
SRR
commands
SPI read
address-data
delay
SPI motion read
address-data
delay
NCS to SCLK active
SCLK to NCS inactive
NCS to MISO high-Z
t
SRAD
250
ns
50
s
t
SRAD-MOT
75
s
t
NCS-SCLK
t
SCLK-NCS
t
NCS-MISO
120
120
250
10
ns
ns
ns
s
SROM download and t
LOAD
frame capture
byte-to-byte delay
NCS to burst mode
exit
Transient Supply
Current
t
BEXIT
4
s
Time NCS must be held high to exit burst mode
I
DDT
85
mA
Max supply current during a V
DD3
ramp from 0 to
3.6V
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
11
PixArt Imaging Inc.
E-mail:
fae_service@pixart.com.tw