LV55D Series 3.3 V
LVDS Clock Oscillators
September 2007
Mechanical:
Inches
A
B
C
D
1
E
1
0.197 +0.006
_
0.125 +0.006
_
0.053 max
0.050
0.050
0.004
0.039
0.025
0.020
0.004R
0.008R
mm
5.00 +0.15
_
3.20 +0.15
_
1.35 max
1.27
1.27
0.10
1.00
0.63
0.50
0.10R
0.20R
1
1
2
6
5
3
4
F
1
G
1
H
1
I
1
Contacts
:
Gold 11.8 µinches 0.3 µm minimum over
Nickel 50 to 350 µinches 1.27 to 8.89 µm
1
Typical dimensions
J
1
K
1
Not to Scale
Pad
1
Function
Output
Enable/Disable
No connect
Ground (GND)
Output
Output*
Supply Voltage
(V
CC
)
Note
When this pad is not connected the oscillator shall operate.
When this pad is <0.30 volts, the output will be inhibited (high impedance state.)
Recommend connecting this pad to V
CC
if the oscillator is to be always on.
There is no internal connection to this pad
2
3
4
5
6
The outputs must be terminated, 100 ohms between the outputs is the ideal
termination.
Recommend connecting appropriate power supply bypass capacitors as close as
possible.
Layout and application information
Recommend connecting Pad 1 and Pad 2 together to permit the design to accept Enable/Disable on both
input pads
For Optimum Jitter Performance, Pletronics recommends:
•
a ground plane under the device
•
no large transient signals (both current and voltage) should be routed under the device
•
do not layout near a large magnetic field such as a high frequency switching power supply
•
do not place near piezoelectric buzzers or mechanical fans.
www.pletronics.com
425-776-1880
6
PLETRONICS [ PLETRONICS, INC. ]
