LV77D Series 2.5 V
LVDS Clock Oscillators
April 2007
Electrical Specification for 2.50V +_10% over the specified temperature range and
the frequency range of 1 to 250 MHz
Item
Min
-50
-25
-20
Max
+50
+25
+20
LVDS
1.60
--
Unit
Condition
ppm
For all supply voltages, load changes, aging for 1
year, shock, vibration and temperatures
Frequency Accuracy “45"
“44"
“20"
Output Waveform
Output High Level
Output Low Level
--
0.90
250
--
Volts
Volts
mVolts
mVolts
Volts
Volts
%
See load circuit R1 = 50 ohms
Differential Output (VOD
)
450
50
Differential Output Error (dVOS)
Output Offset Voltage (VOS)
1.125 1.375
1.125 1.500
> 80 MHz
< 80 MHz
See load circuit R1 = 50 ohms
Output Symmetry
45
55
700
900
0.6
2.8
63
Referenced to 50% of amplitude or crossing point
Vth is 20% and 80% of waveform > 80 MHz
Vth is 20% and 80% of waveform < 80 MHz
Measured from 12KHz to 20MHz from Fnominal
Measured from 10Hz to 1MHz from Fnominal
Output TRISE and TFALL
300
pS
400
pS
Jitter
-
pS RMS
-
-
Vcc Supply Current
mA
mA
Kohm
Volts
Volts
uA
> 80 MHz
Includes current of properly
terminated device
-
40
< 80 MHz
Enable/Disable Internal Pull-up
V disable
50
-
-
To Vcc (equivalent resistance)
Referenced to Ground
0.4
-
V enable
2.0
-10
-10
-
Output leakage
V
OUT = VCC
+10
+10
10
Pad 1 low, device disabled
V
OUT = 0V
uA
Enable
nS
Time for output to reach a logic state
Time for output to reach a high Z state
Disable time
Start up time
-
10
nS
-
5
mS
mS
oC
> 80 MHz
Measured from the time
Vcc = 2.2V
-
3
< 80 MHz
Operating Temperature Range
-10
-40
-55
-
+70
+85
+125
3
Standard Temperature Range
oC
Extended Temperature Range “E” Option
Storage Temperature Range
Standby Current ICC
oC
uA
Pad 1 low, device disabled > 80 MHz
Pad 1 low, device disabled < 80 MHz
-
1.5
mA
Specifications with Pad 1 E/D open circuit
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425-776-1880
3
PLETRONICS [ PLETRONICS, INC. ]
