Pl tronics, Inc.
.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA
Manufacturer of High Quality Frequency Control Products
PECL and LVDS Layout Guidelines
SUGGESTED PCB LAYOUTS
Solder Pad Layout which
accommodates all PECL surface mount
devices
0.200 (5.08)
0 .185
(4.7)
0 .087
(2.2)
'B Pkg'
5 x7
TOP SIDE
BYPASS
BOTTOM
SIDE
BYPASS
0.055 0.100
(1.4) (2.54)
The output line should be designed with proper characteristic
impedance. Pletronics recommends laying out for the larger
'B package' with pads long enough to accept the smaller
5 x 7mm device. This permits the best option for alternate
sources of device. Pletronics also recommends connecting
Pin 1 and Pin 2 together on the models with
Q & QN OUT on pins 4 & 5. This allows
having E/D on either pin 1 or pin 2.
MULTI
LAYER
BYPASS
For Optimum Jitter Performance, Pletronics recommends:
A ground plane under the device with any other signals below the ground plane
Minimize other RF signals near device
No large transient signals (both current and voltage) should be routed under the device
Do not layout near a large magnetic field such as a high frequency switching power supply
Do not place near piezoelectric buzzers or mechancial fans
Reflow Cycle for lead free processing
250
Temperature
°
C
200
150
100
215°C
±
10°C
50 Seconds
175°C
±
10°C
120 to 160 Seconds
260°C max
10 Seconds max
T Rise= 4 Degree/second max
Mar 2004
Pl tronics, Inc.
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com
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PECL, LVDS, OCXO
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PLETRONICS [ PLETRONICS, INC. ]
