SM55G Series 1.8 V
CMOS Clock Oscillators
April 2010
Electrical Specification for 1.80V _+10% over the specified temperature range
Item
Typ
1.5
1.7
1.5
4
Max
3
Unit
nS
Condition
Output TRISE and TFALL
< 35 MHz
CLOAD = 15 pF
20% to 80% of VCC
See Load Circuit
3.5
2.5
7
nS
> 35 MHz and < 70 MHz
> 70 MHz
nS
nS
< 35 MHz
CLOAD = 30 pF
20% to 80% of VCC
See Load Circuit
2
6
6
7
nS
nS
nS
> 35 MHz < 70 MHz
< 35 MHz
12
11
CLOAD = 50 pF
20% to 80% of VCC
See Load Circuit
> 35 MHz and < 45 MHz
VCC Supply Current (ICC)
2
2.5
5
4
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
< 8 MHz
CLOAD = 15 pF
> 8 MHz and < 16 MHz
> 16 MHz and < 35 MHz
> 35 MHz and < 70 MHz
> 70 MHz and < 120 MHz
> 120 MHz
8
-
18
27
37
4.5
5
17
23
2.5
3
< 8 MHz
CLOAD = 30 pF
> 8 MHz and < 16 MHz
> 16 MHz and < 35 MHz
> 35 MHz and < 70 MHz
< 8 MHz
4
8
10
2.5
4
20
4
C
LOAD = 50 pF
6
> 8 MHz and < 16 MHz
> 16 MHz and < 35 MHz
> 35 MHz and < 45 MHz
5
9
13
23
Specifications with Pad 1 E/D open circuit
NOTE: Not specified for 50 pF loads above 45 MHz, or 30 pF loads above 70 MHz
Typical phase noise plot for 5 oscillators at different output frequencies.
0
-20
-40
-60
19.4M
25M
-80
32M
50M
-100
66.7M
-120
-140
-160
-180
10
1,000
100,000
10,000,000
Frequency (Hz)
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425-776-1880
4
PLETRONICS [ PLETRONICS, INC. ]
