Preliminary
PLL600-27/-37
Ultra Low Current XO 10 MHz to 52 MHz
FEATURES
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Low phase noise (-130 dBc @ 10kHz offset).
CMOS output with OE tri-state control.
Selectable oscillator “on” or “off” ( Sleep Mode )
feature in output disable mode
Ultra Low current consumption ( <2mA, <1.5mA
at 27MHz, 3.3V respectively for PLL600-27 and
PLL600-37)
Ultra Low disable mode current (<2uA when
disabled with osc. off)
10 to 52MHz fundamental or 3
rd
OT crystal input.
12mA drive capability at TTL output.
Low jitter (RMS): 2.5ps period jitter.
1.8V, 2.5V and 3.3V DC operation.
Available in 8 pin SOIC, 6 pin SOT or DIE.
PIN ASSIGNMENT (PACKAGE)
8 pin SOIC
XIN/FIN
N/C
GND
OSCSEL^
1
2
3
4
8
7
6
5
XOUT
OE^
VDD
CLK
^ : denotes internal pull-up
6 pin SOT
CLK
GND
XIN/FIN
PLL600-x7
DESCRIPTION
The PLL600-27/-37 form a low cost family of XO
IC’s, designed to consume the lowest current on the
market for the 10MHz to 52MHz range. It accepts
fundamental resonant mode crystal input from 10 to
52MHz. Providing less than -130dBc at 10kHz offset
at 30MHz and with a very low jitter (2.5 ps RMS pe-
riod jitter) makes this chip ideal for applications re-
quiring low current frequency sources.
1
2
3
6
5
4
VDD
OE^
XOUT
^: denotes internal Pull-up
PLL600-x7
BLOCK DIAGRAM
SELECTION TABLE
XIN/FIN
XOUT
XTAL
OSC
CLK
OE
OE^
0
0
1
1
OSCSEL^*
0
1
0
1
OUTPUT
Disabled - osc. off
Disabled - osc. on
Enabled
Enabled
OSCSEL
^ Internal Pull-up, default value is ‘1’ when not connected.
* Not available in 6 pin SOT package.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 1
PLL [ PHASELINK CORPORATION ]
