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P130-69 参数 Datasheet PDF下载

P130-69图片预览
型号: P130-69
PDF下载: 下载PDF文件 查看货源
内容描述: 高速缓冲器译者:单端至PECL或LVDS [High Speed Translator Buffers: Single ended to PECL or LVDS]
分类和应用:
文件页数/大小: 5 页 / 224 K
品牌: PLL [ PHASELINK CORPORATION ]
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PLL130-68/-69
High Speed Translator Buffers: Single ended to PECL or LVDS
PIN DESCRIPTION
Name
NC
REFIN
OECTRL
GND
OESEL
Q_BAR
Q
VDD
Q
Q_BAR
Pin number
1, 3, 4, 6,
8, 12, 14
2
5
7
9
10
11
13
15
16
Type
-
I
I
P
I
O
O
P
O
O
No connection.
Description
Reference input signal. The frequency of this signal will be reproduced
at the output (after translation to PECL or LVDS level).
Output enable input (See OE Logic Table on page 1).
Ground connector.
Output enable logic selector (See OE Logic Table on page 1).
Complementary output. PECL_bar on PLL130-68, LVDS_bar on
PLL130-69.
True output. PECL on PLL130-68, LVDS on PLL130-69.
3.3V Power supply.
Additional true output. PECL on PLL130-68, LVDS on PLL130-69. This
output is the same as pin 11.
Additional complementary output. PECL_bar on PLL130-68, LVDS_bar
on PLL130-69. This output is the same as pin 10.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. General Electrical Specifications
PARAMETERS
Supply Current
(both outputs loaded)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
I
DD
V
DD
CONDITIONS
Fout = 156.25MHz, PECL
Fout = 156.25MHz, LVDS
@ Vdd – 1.3V (PECL)
@ 1.25V (LVDS)
MIN.
45
22
2.97
TYP.
48
25
Same as input
Same as input
±50
MAX.
51
28
3.63
UNITS
mA
V
%
mA
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/29/04 Page 2