PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
4. Jitter and Phase Noise Specifications
PARAMETERS
RMS Period Jitter
(1 sigma – 1000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
CONDITIONS
With capacitive decoupling between
VDD and GND.
36MHz @100Hz offset
36MHz @1kHz offset
36MHz @10kHz offset
36MHz @100kHz offset
36MHz @1MHz offset
MIN.
TYP.
2.5
-80
-110
-130
-138
-145
MAX.
UNITS
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
5. DC Specifications
PARAMETERS
Supply Current, Dynamic,
with Loaded Outputs
Operating Voltage
Output Low Voltage at
CMOS level
Output High Voltage at
CMOS level
Output drive current
Short Circuit Current
VCXO Control Voltage
SYMBOL
I
DD
V
DD
V
OLC
V
OHC
CONDITIONS
F
XIN
= 36MHz
Output load of 15pF
MIN.
TYP.
5
MAX.
6
3.63
0.4
UNITS
mA
V
V
V
2.25
I
OL
= +4mA
I
OH
= -4mA
For V
OL
<0.4V or V
OH
>2.4V
V
DD
– 0.4
8
0
9.5
±50
VCON
V
DD
mA
mA
V
6. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating (VCON = 1.65V)
Maximum Sustainable Drive Level
Operating Drive Level
C0
C0/C1
ESR
SYMBOL
F
XIN
C
L (xtal)
MIN.
17
TYP.
8.5
MAX.
36
200
UNITS
MHz
pF
µW
µW
pF
-
Ω
50
5
250
30
R
S
Note:
The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above.
If the crystal requires more load to be at nominal frequency, the additional load must be added externally.
This however may reduce the pull range.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/08/06 Page 4
PLL [ PHASELINK CORPORATION ]
