PLL502-25
Low Phase Noise VCXO (12MHz to 27MHz)
FEATURES
•
•
•
•
•
•
•
•
Low phase noise VCXO output for the 12MHz to
27MHz range (-135 dBc at 10kHz offset).
CMOS output.
12 to 27MHz crystal input.
Integrated variable capacitors.
Wide pull range (+/- 250 ppm).
Low jitter (RMS): 2.2ps period.
2.5V or 3.3V operation voltage.
Available in 8-Pin SOIC.
PIN CONFIGURATION
XOUT
VDD
VCON
GND
1
2
3
4
8
7
6
5
XIN
N/C
N/C
CLK
PLL502-25
DESCRIPTION
The PLL502-25 is a low cost, high performance and
low phase noise VCXO, providing less than -135dBc
at 10kHz offset in the 12MHz to 27MHz operating
range. The very low jitter (2.2 ps RMS period jitter)
makes this chip ideal for applications requiring volt-
age controlled frequency sources. Input crystal can
range from 12 to 27MHz (fundamental resonant
mode).
OUTPUT RANGE
MULTIPLIER
No PLL
FREQUENCY
RANGE
12 - 27MHz
OUTPUT
BUFFER
CMOS
BLOCK DIAGRAM
XIN
XOUT
XTAL
OSC
VARICAP
CLK
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/17/04 Page 1
PLL [ PHASELINK CORPORATION ]
