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P502-30DC 参数 Datasheet PDF下载

P502-30DC图片预览
型号: P502-30DC
PDF下载: 下载PDF文件 查看货源
内容描述: 750kHz的 - 800MHz的低相位噪声压控石英振荡器( 12 - 25MHz的晶体) [750kHz - 800MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)]
分类和应用: 振荡器晶体石英晶振压控振荡器
文件页数/大小: 8 页 / 213 K
品牌: PLL [ PHASELINK CORPORATION ]
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PLL502-30
750kHz – 800MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals)
FEATURES
750kHz to 800MHz output range.
Low phase noise output (@ 10kHz frequency
offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for
155.52MHz, -115dBc/Hz for 622.08MHz).
Selectable CMOS, PECL and LVDS output.
Selectable High Drive or Standard CMOS.
12 to 25MHz crystal input.
No external load capacitor or varicap required.
Output Enable selector.
Wide pull range (+/-200ppm)
3.3V operation.
Available in DIE (65 mil x 62 mil).
DIE CONFIGURATION
65 mil
OUTSEL0^
OUTSEL1^
SEL0^
SEL1^
VDD
VDD
VDD
VDD
(1550,1475)
17
16
25
24
23
22
21
20
19
18
GNDBUF
CMOS
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
OE_SEL^
XIN
XOUT
SEL3^
62 mil
26
Die ID:
A0505-18
27
15
28
14
13
SEL2^
29
12
11
OE_CTRL
VCON
30
DESCRIPTION
The PLL502-30 is a monolithic low jitter and low
phase noise (-142dBc/Hz @ 10kHz offset) VCXO IC
Die, with CMOS, LVDS and PECL output, covering
the 750kHz to 800MHz output range. It allows the
control of the output frequency with an input voltage
(VCON), using a low cost crystal.
The same die can be used as a VCXO with output
frequencies ranging from F
XIN
/ 16 to F
XIN
x 32
thanks to frequency selector pads. This makes the
PLL502-30 ideal as a universal die for applications
ranging from ADSL to SONET.
C502A
10
31
1
2
3
4
5
6
7
8
9
Y
X
(0,0)
Note: ^ denotes internal pull up
OUTPUT SELECTION AND ENABLE
OUTSEL1
(Pad #18)
0
0
1
1
OUTSEL0
(Pad #25)
0
1
0
1
OE_CTRL
(Pad #30)
Selected Output
High Drive CMOS
Standard CMOS
PECL
LVDS
State
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
OE_SELECT
(Pad #9)
0
BLOCK DIAGRAM
VCO
Divider
Charge
Pump
+
Loop
Filter
VCO
1 (Default)
Pad #9:
0
(Default)
1
0
1
(Default)
Output enabled
Tri-state
Tri-state
Output enabled
Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OE_SELECT is “0”
Logical states defined by CMOS levels if OE_SELECT is “1”
CLKBAR
CLK
SEL
Reference
Divider
XTAL
OSC
VARICAP
Phase
Detector
XIN
XOUT
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/20/06 Page 1
GNDBUF
GND
GND
GND
GND
GND
GND
N/C