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P502-39OCL 参数 Datasheet PDF下载

P502-39OCL图片预览
型号: P502-39OCL
PDF下载: 下载PDF文件 查看货源
内容描述: 750kHz的 - 800MHz的低相位噪声倍频VCXO [750kHz - 800MHz Low Phase Noise Multiplier VCXO]
分类和应用: 石英晶振压控振荡器
文件页数/大小: 9 页 / 257 K
品牌: PLL [ PHASELINK CORPORATION ]
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PLL502-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
FEATURES
Selectable 750kHz to 800MHz range.
Low phase noise output (@ 10kHz frequency
offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for
155.52MHz, -115dBc/Hz for 622.08MHz).
CMOS (PLL502-37), PECL (PLL502-35 and
PLL502-38) or LVDS (PLL502-39) output.
12 to 25MHz crystal input.
No external load capacitor or varicap required.
Output Enable selector.
Wide pull range (+/-200 ppm)
Selectable 1/16 to 32x frequency multiplier.
3.3V operation.
Available in 16-Pin (TSSOP or 3x3mm QFN).
PIN CONFIGURATION
(Top View)
VDD
XIN
XOUT
SEL3^
SEL2^
OE
VCON
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
The PLL502-35 (PECL with inverted OE), PLL502-37
(CMOS), PLL502-38 (PECL), and PLL502-39 (LVDS)
are high performance and low phase noise VCXO IC
chips. They provide phase noise performance as low
as –125dBc at 10kHz offset (at 155MHz), by multi-
plying the input crystal frequency up to 32x. The
wide pull range (+/- 200 ppm) and very low jitter
make them ideal for a wide range of applications,
including SONET/SDH and FEC. They accept fun-
damental parallel resonant mode crystals from 12 to
25MHz.
XOUT
SEL3^
SEL2^
OE
13
14
15
16
12
11
10
SEL1^
9
DESCRIPTION
XIN
SEL0^ / VDD*
VDD / GND*
P502-3x
1
2
3
4
PLL 502-3x
GND
GND
8
7
6
5
GND
CLKC
VDD
CLKT
VCON
BLOCK DIAGRAM
SEL
OE
Vin
X+
X-
Oscillator
Amplifier
w/
integrated
varicaps
PLL
(Phase
Locked
Loop)
^:
*:
Internal pull-up
On 3x3 package, PLL502-35/-38 do not have SEL0 available: Pin
10 is VDD, pin 11 is GND. However, PLL502-37/-39 have SEL0
(pin 10), and pin11 is VDD. See pin assignment table for details.
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL502-38
PLL502-35
PLL502-37
PLL502-39
OE
0 (Default)
1
0
1 (Default)
Tri-state
Tri-state
GND
State
Output enabled
Q
Q
Output enabled
PLL by-pass
PLL502-3x
OE input: Logical states defined by PECL levels for PLL502-38
Logical states defined by CMOS levels for PLL502-37/-39
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/19/06 Page 1